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NJU6820 -1 - 02/08/26 40-common x 128rgb-segment, in 4096-color 4096-color stn lcd driver general description the NJU6820 is a stn lcd driver with 40- common x 128rgb-segment in 4096-color. it consists of 384(128xrgb)-segment segment, 40- common drivers, serial and parallel mpu interface circuits, internal power supply circuits, gradation palettes and 61,440-bit for graphic display data ram. each segment driver outputs 16-gradation level out of 32-gradation level of gradation palette. since the NJU6820 provides a low operating voltage of 1.7v and low operating current, it is ideally suited for battery-powered handheld applications. features 4096-color stn lcd driver lcd drivers 40 commons, 128 rgb-segments, display data ram (ddram) 61,440-bit for graphic display color display mode 16 gradation level out of 32 gradation level of gradation palette black & white display mode 40 x 384 pixels in 16 gradation level or 40 x 384 pixels in b&w display 256-color driving mode 8/16bit parallel interface directly-connective to 68/80 series mpu programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface programmable duty and bias ratios programmable internal voltage booster (maximum 5-times) programmable contrast control using 128-step evr various instructions display data read/write, display on/off, reverse display on/off, all pixels on/off, column address, row address, n-line inversion, initial display line, initial com line, read-modify-write, gradation mode control, increment control, data bus length, discharge on/off, duty cycle ratio, lcd bias ratio, boost level, evr control, power save on/off, etc internal voltage regulator low operating current low logic supply voltage 1.7v to 3.3v lcd driving supply voltage 5.0v to 18.0v c-mos technology rectangle out look for cog package bumped chip / tcp preliminary package outline NJU6820cj
NJU6820 - 2 - pad location chip center :x=0um, y=0um chip size :x=18.86mm, y= 2.39mm chip thickness :625um + 25um bump pitch :42um(min) bump size :24um x 140um bump hight :17.5um(typ) bump material :au ( -9062 m 25 m 50 m 50 m 50 m 50 m 20 m ali g nment mark 1 a li g nment mark coordinates ali g nment mark 2 a li g nment mark coordinates ali g nment mark 3 dmy 102 x dmy 99 dmy 87 dmy 85 dmy 88 dmy 90 com 39 com 20 v ssa c4- c4- c4+ c4+ c3- c3- c3+ c3+ c2- c2- c2+ c2+ c1+ c1+ c1- v ss a dmy 7 dmy 6 v dd a sega 127 segb 127 segc 127 sega 0 segb 0 segc 0 com 38 com 37 com 36 com 24 com 23 com 21 com 0 com 19 com 1 com 2 com 3 com 16 com 17 com 18 dmy 1 dmy 2 dmy 3 sel68 dmy 4 dmy 5 ps 1 resb dmy 8 dmy 9 dmy 10 csb dmy 11 dmy 12 dmy 13 rs dmy 15 dmy 16 dmy 14 wrb dmy 17 dmy 18 dmy 19 rdb dmy 20 v dd a dmy 21 d 0 dmy 22 dmy 23 d 1 dmy 25 d 2 dmy 24 dmy 26 dmy 27 d 3 dmy 28 dmy 29 d 4 dmy 30 dmy 31 d 5 dmy 32 d 6 dmy 34 dmy 33 dmy 35 d 7 dmy 36 v ss a dmy 37 dmy 38 dmy 39 d 8 d 9 dmy 40 dmy 41 d 10 dmy 42 dmy 43 d 11 dmy 44 dmy 45 d 12 dmy 47 d 13 dmy 46 dmy 49 v dd dmy 54 dmy 53 dmy 51 dmy 48 clk d 14 dmy 50 d 15 dmy 52 v dd dmy 55 cl dmy 56 flm dmy 58 dmy 59 fr dmy 60 dmy 62 dmy 61 dmy 63 dmy 64 osc 2 dmy 65 v ss dmy 66 v lcd v lcd dmy 67 v 1 v 1 v 2 v 2 dmy 68 v 3 v 3 v 4 v 4 v reg dmy 69 v reg dmy 70 v ref dmy 71 dmy 72 v ss v out v out dmy 73 v ee v ee dmy 74 dmy 57 osc 1 v ss v ref v b a v b a v ss dmy 75 c1- dmy 76 dmy 77 dmy 78 dmy 79 dmy 80 dmy 81 dmy 82 dmy 83 dmy 84 dmy 93 dmy 91 dmy 96 dmy 94 dmy 97 dmy 100 y
NJU6820 -3 - pad coordinates 1 chip size 18860 m x 2390 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 1 dmy 0 -8967 -990 51 dmy 24 -6699 -990 101 dmy 48 -3507 -990 2 dmy 1 -8925 -990 52 dmy 25 -6573 -990 102 dmy 49 -3381 -990 3 dmy 2 -8883 -990 53 d 2 -6531 -990 103 d 14 -3339 -990 4 v ssa -8841 -990 54 d 2 -6489 -990 104 d 14 -3297 -990 5 v ssa -8799 -990 55 dmy 26 -6447 -990 105 dmy 50 -3255 -990 6 dmy 3 -8757 -990 56 dmy 27 -6321 -990 106 dmy 51 -3129 -990 7 sel68 -8715 -990 57 d 3 -6279 -990 107 d 15 -3087 -990 8 sel68 -8673 -990 58 d 3 -6237 -990 108 d 15 -3045 -990 9 dmy 4 -8631 -990 59 dmy 28 -6195 -990 109 dmy 52 -3003 -990 10 v dda -8589 -990 60 dmy 29 -6069 -990 110 dmy 53 -2877 -990 11 v dda -8547 -990 61 d 4 -6027 -990 111 v dd -2835 -990 12 dmy 5 -8505 -990 62 d 4 -5985 -990 112 v dd -2793 -990 13 ps -8463 -990 63 dmy 30 -5943 -990 113 v dd -2751 -990 14 ps -8421 -990 64 dmy 31 -5817 -990 114 v dd -2709 -990 15 dmy 6 -8379 -990 65 d 5 -5775 -990 115 v dd -2667 -990 16 v ssa -8337 -990 66 d 5 -5733 -990 116 v dd -2625 -990 17 v ssa -8295 -990 67 dmy 32 -5691 -990 117 v dd -2583 -990 18 dmy 7 -8253 -990 68 dmy 33 -5565 -990 118 v dd -2541 -990 19 resb -8211 -990 69 d 6 -5523 -990 119 v dd -2499 -990 20 resb -8169 -990 70 d 6 -5481 -990 120 v dd -2457 -990 21 dmy 8 -8127 -990 71 dmy 34 -5439 -990 121 v dd -2415 -990 22 dmy 9 -8085 -990 72 dmy 35 -5313 -990 122 dmy 54 -2289 -990 23 dmy 10 -8043 -990 73 d 7 -5271 -990 123 dmy 55 -2163 -990 24 csb -8001 -990 74 d 7 -5229 -990 124 cl -2121 -990 25 csb -7959 -990 75 dmy 36 -5187 -990 125 cl -2079 -990 26 dmy 11 -7917 -990 76 v ssa -5061 -990 126 dmy 56 -2037 -990 27 dmy 12 -7875 -990 77 v ssa -5019 -990 127 dmy 57 -1911 -990 28 dmy 13 -7833 -990 78 dmy 37 -4893 -990 128 flm -1869 -990 29 rs -7791 -990 79 d 8 -4851 -990 129 flm -1827 -990 30 rs -7749 -990 80 d 8 -4809 -990 130 dmy 58 -1785 -990 31 dmy 14 -7707 -990 81 dmy 38 -4767 -990 131 dmy 59 -1659 -990 32 dmy 15 -7665 -990 82 dmy 39 -4641 -990 132 fr -1617 -990 33 dmy 16 -7623 -990 83 d 9 -4599 -990 133 fr -1575 -990 34 wrb -7581 -990 84 d 9 -4557 -990 134 dmy 60 -1533 -990 35 wrb -7539 -990 85 dmy 40 -4515 -990 135 dmy 61 -1407 -990 36 dmy 17 -7497 -990 86 dmy 41 -4389 -990 136 clk -1365 -990 37 dmy 18 -7455 -990 87 d 10 -4347 -990 137 clk -1323 -990 38 dmy 19 -7413 -990 88 d 10 -4305 -990 138 dmy 62 -1281 -990 39 rdb -7371 -990 89 dmy 42 -4263 -990 139 dmy 63 -1155 -990 40 rdb -7329 -990 90 dmy 43 -4137 -990 140 osc 1 -1113 -990 41 dmy 20 -7287 -990 91 d 11 -4095 -990 141 osc 1 -1071 -990 42 v dda -7245 -990 92 d 11 -4053 -990 142 dmy 64 -1029 -990 43 v dda -7203 -990 93 dmy 44 -4011 -990 143 osc 2 -903 -990 44 dmy 21 -7077 -990 94 dmy 45 -3885 -990 144 osc 2 -861 -990 45 d 0 -7035 -990 95 d 12 -3843 -990 145 dmy 65 -735 -990 46 d 0 -6993 -990 96 d 12 -3801 -990 146 v ss -693 -990 47 dmy 22 -6951 -990 97 dmy 46 -3759 -990 147 v ss -651 -990 48 dmy 23 -6825 -990 98 dmy 47 -3633 -990 148 v ss -609 -990 49 d 1 -6783 -990 99 d 13 -3591 -990 149 v ss -567 -990 50 d 1 -6741 -990 100 d 13 -3549 -990 150 v ss -525 -990
NJU6820 - 4 - pad coordinates 2 chip size 18860 m x 2390 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 151 v ss -483 -990 201 v 4 1953 -990 251 v out 4179 -990 152 v ss -441 -990 202 v 4 1995 -990 252 v out 4221 -990 153 v ss -399 -990 203 v 4 2037 -990 253 v out 4263 -990 154 v ss -357 -990 204 v 4 2079 -990 254 v out 4305 -990 155 v ss -315 -990 205 dmy 69 2121 -990 255 v out 4347 -990 156 v ss -273 -990 206 v reg 2163 -990 256 v out 4389 -990 157 dmy 66 -147 -990 207 v reg 2205 -990 257 v out 4431 -990 158 v lcd -21 -990 208 v reg 2247 -990 258 v out 4473 -990 159 v lcd 21 -990 209 v reg 2289 -990 259 dmy 73 4641 -990 160 v lcd 63 -990 210 v reg 2331 -990 260 v ee 4683 -990 161 v lcd 105 -990 211 v reg 2373 -990 261 v ee 4725 -990 162 v lcd 147 -990 212 v reg 2415 -990 262 v ee 4767 -990 163 v lcd 189 -990 213 v reg 2457 -990 263 v ee 4809 -990 164 v lcd 231 -990 214 v reg 2499 -990 264 v ee 4851 -990 165 v lcd 273 -990 215 v reg 2541 -990 265 v ee 4893 -990 166 v lcd 315 -990 216 dmy 70 2583 -990 266 v ee 4935 -990 167 dmy 67 357 -990 217 v ref 2625 -990 267 v ee 4977 -990 168 v 1 399 -990 218 v ref 2667 -990 268 v ee 5019 -990 169 v 1 441 -990 219 v ref 2709 -990 269 v ee 5061 -990 170 v 1 483 -990 220 v ref 2751 -990 270 dmy 74 5187 -990 171 v 1 525 -990 221 v ref 2793 -990 271 c1+ 5229 -990 172 v 1 567 -990 222 v ref 2835 -990 272 c1+ 5271 -990 173 v 1 609 -990 223 v ref 2877 -990 273 c1+ 5313 -990 174 v 1 651 -990 224 v ref 2919 -990 274 c1+ 5355 -990 175 v 1 693 -990 225 v ref 2961 -990 275 c1+ 5397 -990 176 v 1 735 -990 226 v ref 3003 -990 276 c1+ 5439 -990 177 v 2 861 -990 227 dmy 71 3045 -990 277 c1+ 5481 -990 178 v 2 903 -990 228 v ba 3087 -990 278 c1+ 5523 -990 179 v 2 945 -990 229 v ba 3129 -990 279 c1+ 5565 -990 180 v 2 987 -990 230 v ba 3171 -990 280 c1+ 5607 -990 181 v 2 1029 -990 231 v ba 3213 -990 281 dmy 75 5649 -990 182 v 2 1071 -990 232 v ba 3255 -990 282 c1- 5691 -990 183 v 2 1113 -990 233 v ba 3297 -990 283 c1- 5733 -990 184 v 2 1155 -990 234 v ba 3339 -990 284 c1- 5775 -990 185 v 2 1197 -990 235 v ba 3381 -990 285 c1- 5817 -990 186 dmy 68 1239 -990 236 v ba 3423 -990 286 c1- 5859 -990 187 v 3 1281 -990 237 v ba 3465 -990 287 c1- 5901 -990 188 v 3 1323 -990 238 dmy 72 3507 -990 288 c1- 5943 -990 189 v 3 1365 -990 239 v ss 3549 -990 289 c1- 5985 -990 190 v 3 1407 -990 240 v ss 3591 -990 290 c1- 6027 -990 191 v 3 1449 -990 241 v ss 3633 -990 291 c1- 6069 -990 192 v 3 1491 -990 242 v ss 3675 -990 292 dmy 76 6111 -990 193 v 3 1533 -990 243 v ss 3717 -990 293 c2+ 6153 -990 194 v 3 1575 -990 244 v ss 3759 -990 294 c2+ 6195 -990 195 v 3 1617 -990 245 v ss 3801 -990 295 c2+ 6237 -990 196 v 4 1743 -990 246 v ss 3843 -990 296 c2+ 6279 -990 197 v 4 1785 -990 247 v ss 3885 -990 297 c2+ 6321 -990 198 v 4 1827 -990 248 v ss 3927 -990 298 c2+ 6363 -990 199 v 4 1869 -990 249 v out 4095 -990 299 c2+ 6405 -990 200 v 4 1911 -990 250 v out 4137 -990 300 c2+ 6447 -990
NJU6820 -5 - pad coordinates 3 chip size 18860 m x 2390 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 301 c2+ 6489 -990 351 c4- 8589 -990 401 sega 3 7665 990 302 c2+ 6531 -990 352 c4- 8631 -990 402 segb 3 7623 990 303 dmy 77 6573 -990 353 c4- 8673 -990 403 segc 3 7581 990 304 c2- 6615 -990 354 c4- 8715 -990 404 sega 4 7539 990 305 c2- 6657 -990 355 c4- 8757 -990 405 segb 4 7497 990 306 c2- 6699 -990 356 c4- 8799 -990 406 segc 4 7455 990 307 c2- 6741 -990 357 c4- 8841 -990 407 sega 5 7413 990 308 c2- 6783 -990 358 dmy 82 8883 -990 408 segb 5 7371 990 309 c2- 6825 -990 359 dmy 83 8925 -990 409 segc 5 7329 990 310 c2- 6867 -990 360 dmy 84 8967 -990 410 sega 6 7287 990 311 c2- 6909 -990 361 dmy 85 9225 -910 411 segb 6 7245 990 312 c2- 6951 -990 362 dmy 86 9225 -868 412 segc 6 7203 990 313 c2- 6993 -990 363 dmy 86 9225 -826 413 sega 7 7161 990 314 dmy 78 7035 -990 364 dmy 86 9225 -784 414 segb 7 7119 990 315 c3+ 7077 -990 365 dmy 87 9225 -742 415 segc 7 7077 990 316 c3+ 7119 -990 366 dmy 88 9135 990 416 sega 8 7035 990 317 c3+ 7161 -990 367 dmy 89 9093 990 417 segb 8 6993 990 318 c3+ 7203 -990 368 dmy 90 9051 990 418 segc 8 6951 990 319 c3+ 7245 -990 369 com 19 9009 990 419 sega 9 6909 990 320 c3+ 7287 -990 370 com 18 8967 990 420 segb 9 6867 990 321 c3+ 7329 -990 371 com 17 8925 990 421 segc 9 6825 990 322 c3+ 7371 -990 372 com 16 8883 990 422 sega 10 6783 990 323 c3+ 7413 -990 373 com 15 8841 990 423 segb 10 6741 990 324 c3+ 7455 -990 374 com 14 8799 990 424 segc 10 6699 990 325 dmy 79 7497 -990 375 com 13 8757 990 425 sega 11 6657 990 326 c3- 7539 -990 376 com 12 8715 990 426 segb 11 6615 990 327 c3- 7581 -990 377 com 11 8673 990 427 segc 11 6573 990 328 c3- 7623 -990 378 com 10 8631 990 428 sega 12 6531 990 329 c3- 7665 -990 379 com 9 8589 990 429 segb 12 6489 990 330 c3- 7707 -990 380 com 8 8547 990 430 segc 12 6447 990 331 c3- 7749 -990 381 com 7 8505 990 431 sega 13 6405 990 332 c3- 7791 -990 382 com 6 8463 990 432 segb 13 6363 990 333 c3- 7833 -990 383 com 5 8421 990 433 segc 13 6321 990 334 c3- 7875 -990 384 com 4 8379 990 434 sega 14 6279 990 335 c3- 7917 -990 385 com 3 8337 990 435 segb 14 6237 990 336 dmy 80 7959 -990 386 com 2 8295 990 436 segc 14 6195 990 337 c4+ 8001 -990 387 com 1 8253 990 437 sega 15 6153 990 338 c4+ 8043 -990 388 com 0 8211 990 438 segb 15 6111 990 339 c4+ 8085 -990 389 dmy 91 8169 990 439 segc 15 6069 990 340 c4+ 8127 -990 390 dmy 92 8127 990 440 sega 16 6027 990 341 c4+ 8169 -990 391 dmy 93 8085 990 441 segb 16 5985 990 342 c4+ 8211 -990 392 sega 0 8043 990 442 segc 16 5943 990 343 c4+ 8253 -990 393 segb 0 8001 990 443 sega 17 5901 990 344 c4+ 8295 -990 394 segc 0 7959 990 444 segb 17 5859 990 345 c4+ 8337 -990 395 sega 1 7917 990 445 segc 17 5817 990 346 c4+ 8379 -990 396 segb 1 7875 990 446 sega 18 5775 990 347 dmy 81 8421 -990 397 segc 1 7833 990 447 segb 18 5733 990 348 c4- 8463 -990 398 sega 2 7791 990 448 segc 18 5691 990 349 c4- 8505 -990 399 segb 2 7749 990 449 sega 19 5649 990 350 c4- 8547 -990 400 segc 2 7707 990 450 segb 19 5607 990
NJU6820 - 6 - pad coordinates 4 chip size 18860 m x 2390 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 451 segc 19 5565 990 501 segb 36 3465 990 551 sega 53 1365 990 452 sega 20 5523 990 502 segc 36 3423 990 552 segb 53 1323 990 453 segb 20 5481 990 503 sega 37 3381 990 553 segc 53 1281 990 454 segc 20 5439 990 504 segb 37 3339 990 554 sega 54 1239 990 455 sega 21 5397 990 505 segc 37 3297 990 555 segb 54 1197 990 456 segb 21 5355 990 506 sega 38 3255 990 556 segc 54 1155 990 457 segc 21 5313 990 507 segb 38 3213 990 557 sega 55 1113 990 458 sega 22 5271 990 508 segc 38 3171 990 558 segb 55 1071 990 459 segb 22 5229 990 509 sega 39 3129 990 559 segc 55 1029 990 460 segc 22 5187 990 510 segb 39 3087 990 560 sega 56 987 990 461 sega 23 5145 990 511 segc 39 3045 990 561 segb 56 945 990 462 segb 23 5103 990 512 sega 40 3003 990 562 segc 56 903 990 463 segc 23 5061 990 513 segb 40 2961 990 563 sega 57 861 990 464 sega 24 5019 990 514 segc 40 2919 990 564 segb 57 819 990 465 segb 24 4977 990 515 sega 41 2877 990 565 segc 57 777 990 466 segc 24 4935 990 516 segb 41 2835 990 566 sega 58 735 990 467 sega 25 4893 990 517 segc 41 2793 990 567 segb 58 693 990 468 segb 25 4851 990 518 sega 42 2751 990 568 segc 58 651 990 469 segc 25 4809 990 519 segb 42 2709 990 569 sega 59 609 990 470 sega 26 4767 990 520 segc 42 2667 990 570 segb 59 567 990 471 segb 26 4725 990 521 sega 43 2625 990 571 segc 59 525 990 472 segc 26 4683 990 522 segb 43 2583 990 572 sega 60 483 990 473 sega 27 4641 990 523 segc 43 2541 990 573 segb 60 441 990 474 segb 27 4599 990 524 sega 44 2499 990 574 segc 60 399 990 475 segc 27 4557 990 525 segb 44 2457 990 575 sega 61 357 990 476 sega 28 4515 990 526 segc 44 2415 990 576 segb 61 315 990 477 segb 28 4473 990 527 sega 45 2373 990 577 segc 61 273 990 478 segc 28 4431 990 528 segb 45 2331 990 578 sega 62 231 990 479 sega 29 4389 990 529 segc 45 2289 990 579 segb 62 189 990 480 segb 29 4347 990 530 sega 46 2247 990 580 segc 62 147 990 481 segc 29 4305 990 531 segb 46 2205 990 581 sega 63 105 990 482 sega 30 4263 990 532 segc 46 2163 990 582 segb 63 63 990 483 segb 30 4221 990 533 sega 47 2121 990 583 segc 63 21 990 484 segc 30 4179 990 534 segb 47 2079 990 584 sega 64 -21 990 485 sega 31 4137 990 535 segc 47 2037 990 585 segb 64 -63 990 486 segb 31 4095 990 536 sega 48 1995 990 586 segc 64 -105 990 487 segc 31 4053 990 537 segb 48 1953 990 587 sega 65 -147 990 488 sega 32 4011 990 538 segc 48 1911 990 588 segb 65 -189 990 489 segb 32 3969 990 539 sega 49 1869 990 589 segc 65 -231 990 490 segc 32 3927 990 540 segb 49 1827 990 590 sega 66 -273 990 491 sega 33 3885 990 541 segc 49 1785 990 591 segb 66 -315 990 492 segb 33 3843 990 542 sega 50 1743 990 592 segc 66 -357 990 493 segc 33 3801 990 543 segb 50 1701 990 593 sega 67 -399 990 494 sega 34 3759 990 544 segc 50 1659 990 594 segb 67 -441 990 495 segb 34 3717 990 545 sega 51 1617 990 595 segc 67 -483 990 496 segc 34 3675 990 546 segb 51 1575 990 596 sega 68 -525 990 497 sega 35 3633 990 547 segc 51 1533 990 597 segb 68 -567 990 498 segb 35 3591 990 548 sega 52 1491 990 598 segc 68 -609 990 499 segc 35 3549 990 549 segb 52 1449 990 599 sega 69 -651 990 500 sega 36 3507 990 550 segc 52 1407 990 600 segb 69 -693 990
NJU6820 -7 - pad coordinates 5 chip size 18860 m x 2390 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 601 segc 69 -735 990 651 segb 86 -2835 990 701 sega 103 -4935 990 602 sega 70 -777 990 652 segc 86 -2877 990 702 segb 103 -4977 990 603 segb 70 -819 990 653 sega 87 -2919 990 703 segc 103 -5019 990 604 segc 70 -861 990 654 segb 87 -2961 990 704 sega 104 -5061 990 605 sega 71 -903 990 655 segc 87 -3003 990 705 segb 104 -5103 990 606 segb 71 -945 990 656 sega 88 -3045 990 706 segc 104 -5145 990 607 segc 71 -987 990 657 segb 88 -3087 990 707 sega 105 -5187 990 608 sega 72 -1029 990 658 segc 88 -3129 990 708 segb 105 -5229 990 609 segb 72 -1071 990 659 sega 89 -3171 990 709 segc 105 -5271 990 610 segc 72 -1113 990 660 segb 89 -3213 990 710 sega 106 -5313 990 611 sega 73 -1155 990 661 segc 89 -3255 990 711 segb 106 -5355 990 612 segb 73 -1197 990 662 sega 90 -3297 990 712 segc 106 -5397 990 613 segc 73 -1239 990 663 segb 90 -3339 990 713 sega 107 -5439 990 614 sega 74 -1281 990 664 segc 90 -3381 990 714 segb 107 -5481 990 615 segb 74 -1323 990 665 sega 91 -3423 990 715 segc 107 -5523 990 616 segc 74 -1365 990 666 segb 91 -3465 990 716 sega 108 -5565 990 617 sega 75 -1407 990 667 segc 91 -3507 990 717 segb 108 -5607 990 618 segb 75 -1449 990 668 sega 92 -3549 990 718 segc 108 -5649 990 619 segc 75 -1491 990 669 segb 92 -3591 990 719 sega 109 -5691 990 620 sega 76 -1533 990 670 segc 92 -3633 990 720 segb 109 -5733 990 621 segb 76 -1575 990 671 sega 93 -3675 990 721 segc 109 -5775 990 622 segc 76 -1617 990 672 segb 93 -3717 990 722 sega 110 -5817 990 623 sega 77 -1659 990 673 segc 93 -3759 990 723 segb 110 -5859 990 624 segb 77 -1701 990 674 sega 94 -3801 990 724 segc 110 -5901 990 625 segc 77 -1743 990 675 segb 94 -3843 990 725 sega 111 -5943 990 626 sega 78 -1785 990 676 segc 94 -3885 990 726 segb 111 -5985 990 627 segb 78 -1827 990 677 sega 95 -3927 990 727 segc 111 -6027 990 628 segc 78 -1869 990 678 segb 95 -3969 990 728 sega 112 -6069 990 629 sega 79 -1911 990 679 segc 95 -4011 990 729 segb 112 -6111 990 630 segb 79 -1953 990 680 sega 96 -4053 990 730 segc 112 -6153 990 631 segc 79 -1995 990 681 segb 96 -4095 990 731 sega 113 -6195 990 632 sega 80 -2037 990 682 segc 96 -4137 990 732 segb 113 -6237 990 633 segb 80 -2079 990 683 sega 97 -4179 990 733 segc 113 -6279 990 634 segc 80 -2121 990 684 segb 97 -4221 990 734 sega 114 -6321 990 635 sega 81 -2163 990 685 segc 97 -4263 990 735 segb 114 -6363 990 636 segb 81 -2205 990 686 sega 98 -4305 990 736 segc 114 -6405 990 637 segc 81 -2247 990 687 segb 98 -4347 990 737 sega 115 -6447 990 638 sega 82 -2289 990 688 segc 98 -4389 990 738 segb 115 -6489 990 639 segb 82 -2331 990 689 sega 99 -4431 990 739 segc 115 -6531 990 640 segc 82 -2373 990 690 segb 99 -4473 990 740 sega 116 -6573 990 641 sega 83 -2415 990 691 segc 99 -4515 990 741 segb 116 -6615 990 642 segb 83 -2457 990 692 sega 100 -4557 990 742 segc 116 -6657 990 643 segc 83 -2499 990 693 segb 100 -4599 990 743 sega 117 -6699 990 644 sega 84 -2541 990 694 segc 100 -4641 990 744 segb 117 -6741 990 645 segb 84 -2583 990 695 sega 101 -4683 990 745 segc 117 -6783 990 646 segc 84 -2625 990 696 segb 101 -4725 990 746 sega 118 -6825 990 647 sega 85 -2667 990 697 segc 101 -4767 990 747 segb 118 -6867 990 648 segb 85 -2709 990 698 sega 102 -4809 990 748 segc 118 -6909 990 649 segc 85 -2751 990 699 segb 102 -4851 990 749 sega 119 -6951 990 650 sega 86 -2793 990 700 segc 102 -4893 990 750 segb 119 -6993 990
NJU6820 - 8 - pad coordinates 6 chip size 18860 m x 2390 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) pad no. terminal x( m) y( m) 751 segc 119 -7035 990 801 dmy 99 -9135 990 752 sega 120 -7077 990 802 dmy 100 -9225 -742 753 segb 120 -7119 990 803 dmy 101 -9225 -784 754 segc 120 -7161 990 804 dmy 101 -9225 -826 755 sega 121 -7203 990 805 dmy 101 -9225 -868 756 segb 121 -7245 990 806 dmy 102 -9225 -910 757 segc 121 -7287 990 801 dmy 99 -9135 990 758 sega 122 -7329 990 802 dmy 100 -9225 -742 759 segb 122 -7371 990 803 dmy 101 -9225 -784 760 segc 122 -7413 990 804 dmy 101 -9225 -826 761 sega 123 -7455 990 805 dmy 101 -9225 -868 762 segb 123 -7497 990 806 dmy 102 -9225 -910 763 segc 123 -7539 990 801 dmy 99 -9135 990 764 sega 124 -7581 990 802 dmy 100 -9225 -742 765 segb 124 -7623 990 766 segc 124 -7665 990 767 sega 125 -7707 990 768 segb 125 -7749 990 769 segc 125 -7791 990 770 sega 126 -7833 990 771 segb 126 -7875 990 772 segc 126 -7917 990 773 sega 127 -7959 990 774 segb 127 -8001 990 775 segc 127 -8043 990 776 dmy 94 -8085 990 777 dmy 95 -8127 990 778 dmy 96 -8169 990 779 com 20 -8211 990 780 com 21 -8253 990 781 com 22 -8295 990 782 com 23 -8337 990 783 com 24 -8379 990 784 com 25 -8421 990 785 com 26 -8463 990 786 com 27 -8505 990 787 com 28 -8547 990 788 com 29 -8589 990 789 com 30 -8631 990 790 com 31 -8673 990 791 com 32 -8715 990 792 com 33 -8757 990 793 com 34 -8799 990 794 com 35 -8841 990 795 com 36 -8883 990 796 com 37 -8925 990 797 com 38 -8967 990 798 com 39 -9009 990 799 dmy 97 -9051 990 800 dmy 98 -9093 990
NJU6820 -9 - block diagram rs p/s sel68 csb wrb rdb v dda v dd v lcd , v 1 -v 4 v out v ba v ee mpu interface bus holder internal bus column address decoder display timing generator display data ram (dd ram) 128x40x(4+4+4)bit segment driver clk fr flm cl common driver 5 c1- c1+ c2+ c2- v ref c3+ c3- c4+ c4- sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 com 39 gradation circuit data latch circuit shift register column address counter column address register d 7 d 4 /spol d 6 d 15 d 14 d 13 d 12 d 5 d 11 d 10 d 9 d 8 d 3 /smode d 0 /scl d 2 d 1 /sda ram interface pole control instruction decoder osc 1 register read control oscillator v ssa osc 2 v reg voltage regulator voltage booster sega 1 segb 1 segc 1 sega 126 segb 126 segc 126 com 0 v ss v ssh line counter line address decoder row address decoder initial display line register row address register row address counter i/o buffer resb reset
NJU6820 - 10 - power supply circuits block diagram v ba v ref v out v ee voltage booster c1+ c1- c2+ c2- c3+ c3- c4+ c4- v reg + - + - + - + - + - reference voltage generator boost level register evr register v 1 v 2 v 3 v 4 v lcd + - gain control (1x-5x) + - voltage regulator e.v.r 1/2v reg
NJU6820 - 11 - terminal description 1 no. symbol i/o function 111-121 v dd power power supply for logic circuits 146-156 v ss power gnd for logic circuits 239-248 v ssh power gnd for high voltage circuits 10,11, 42,43, v dda power this terminal is internally connected to the v dd level. ? this terminal is used to fix the selection terminals to the v dd level. note) do not use this terminal for a main power supply. 4,5, 16,17, 76,77, v ssa power this terminal is internally connected to the v ss level. ? this terminal is used to fix the selection terminals to the v ss level. note) do not use this terminal for a main gnd. 158-166 168-176 177-185 187-195 196-204 v lcd v 1 v 2 v 3 v 4 power/o lcd driving voltages ? when the internal voltage booster is not used, external lcd driving voltages (v 1 to v 4 and v lcd ) must be supplied on these terminals. the external voltages must be maintained with the following relation. v ss NJU6820 - 12 - terminal description 2 no. symbol i/o function 45,46 d 0 /scl i/o 49,50 d 1 /sda i/o 57,58 d 3 /smode i/o 61,62 d 4 /spol i/o 53,54 65,66 69,70 73,74 d 2 d 5 d 6 d 7 i/o parallel interface: d 7 to d 0 : 8-bit bi-directional bus ? in the parallel interface mode (p/s=?1?), these terminals connect to 8-bit bi-directional mpu bus. serial interface: sda : serial data scl : serial clock smode : 3-/4-line serial interface mode selection spol : rs polarity selection (in the 3-line serial interface mode) ? in the 3-/4-line serial interface mode (p/s=?0?), the d0 terminal is assigned to the scl and the d 1 terminal to the sda. ? in the 3-line serial interface mode, the d 4 terminal is assigned to the spol. ? serial data on the sda is fetched at the rising edge of the scl signal in the order of the d 7 , d 6 ?d 0 , and the fetched data is converted into 8-bit parallel data at the falling edge of the 8th scl signal. ? the scl signal must be set to ?0? after data transmissions or during non-access. 79,80 83,84 87,88 91,92 95,96 99,100 103,104 107,108 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 i/o 8-bit bi-directional bus ? in the 16-bit data bus mode, these terminals are assigned to the upper 8-bit data bus. ? in the serial interface mode or 8-bit data bus mode of the parallel interface, these terminals must be fixed to ?1? or ?0?. 24,25 csb i chip select active ?0? resister select ? this signal distinguishes transferred data as an instruction or display data as follows. rs h l distinct. instruction display data 29,30 rs i 39,40 rdb (e) i 80 series mpu interface (p/s=?1?, sel68=?0?) rdb signal. active ?l?. 68 series mpu interface (p/s=?1?, sel68=?1?) enable signal. active ?h?. 80 series mpu interface (p/s=?1?, sel68=?0?) wrb signal. active ?l?. 68 series mpu interface (p/s=?1?, sel68=?1?) r/w signal. r/w h l status read write 34,35 wrb (r/w) i
NJU6820 - 13 - terminal description 3 no. symbol i/o function parallel / serial interface mode selection p/s chip select data/ instruction data read/write serial clock h csb rs d 0 ~ d 7 rdb, wrb - l csb rs sda (d 1 ) write only scl (d 0 ) 13,14 p/s i ? since the d 15 to d 5 and d 2 terminals are in the high impedance in the serial inter face mode (p/s=?0?), they must be fixed to ?1? or ?0?. the rdb and wrb terminals also must be ?1? or ?0?. 124,125 cl o this terminal must be opened. 128,129 flm o this terminal must be opened. 132,133 fr o this terminal must be opened. 136,137 clk o this terminal must be opened. 140,141 143,144 osc 1 osc 2 i o osc ? when the internal oscillator clock is used, osc 1 terminal must be fixed to ?1? or ?0?, and the osc 2 terminal must be opened. when the oscillation frequency from the internal oscillator is adjusted by an external resistor between osc 1 terminal and osc 2 . ? when an external oscillator is used, external clock is input to the osc 1 terminal or an external resistor is connected between the osc 1 and osc 2 terminals.
NJU6820 - 14 - terminal description 4 no. symbol i/o function segment output rev mode turn-off turn-on normal 0 1 reverse 1 0 ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and display data. in the b/w mode fr signal display data normal display mode v 2 v lcd v 3 v ss reverse display mode v lcd v 2 v ss v 3 392-775 sega 0 - sega 127 , segb 0 - segb 127 , segc 0 - segc 127 o common output these terminals output lcd driving waveforms in accordance with the combination of the fr signal and scanning data. data fr output level h h v ss l h v 1 h l v lcd l l v 4 369-388, 779-798, com 0 -com 39 o terminal no. 1-3, 12, 18, 21-23, 26-28, 31-33, 36-38, 41, 47, 48, 51, 52, 55, 56, 59, 60, 63, 64, 67, 68, 71, 72, 75, 81, 82, 85, 86, 89, 90, 93, 94, 97, 98, 101, 102, 105, 106, 109, 110, 122, 123, 126, 127, 130, 131, 134, 135, 138, 139, 142, 145, 157, 167, 186, 205, 216, 227, 238, 259, 270, 281, 292, 314, 325, 336, 347, 358- 368, 389-391, 776-778, 799-806 are dummy.)
NJU6820 - 15 - functional description (1) mpu interface (1-1) selection of parallel / serial interface mode select the p/s terminal is used to select parallel or serial interface mode as shown in the following table. in the serial interface mode, it is possible to read out display data from the ddram and status from the internal registers. table1 p/s p/s mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d 7 -d 0 (d 15 -d 0 ) l serial i/f csb rs - - - sda scl - note 1) ? -? : fix to ?1? or ?0?. (1-2) selection of mpu interface type in the parallel interface mode, the sel68 terminal is used to select 68- or 80-series mpu interface type as shown in the following table. table2 sel68 mpu type csb rs rdb wrb data h 68 series mpu csb rs e r/w d 7 -d 0 (d 15 -d 0 ) l 80 series mpu csb rs rdb wrb d 7 -d 0 (d 15 -d 0 ) (1-3) data distinction in the parallel interface mode, the combination of rs, rdb, and wrb (r/w) signals distinguishes transferred data between the lsi and mpu as instruction or display data, as shown in the following table. table3 68 series 80 series rs r/w rdb wrb function h h l h read out instruction data h l h l write instruction data l h l h read out display data l l h l write display data (1-4) selection of serial interface mode in the serial interface mode, the smode terminal is used to select the 3- or 4-line serial interface mode as shown in the following table. table4 smode serial interface mode h 3-line l 4-line
NJU6820 - 16 - (1-5) 4-line serial interface mode in the 4-line serial interface mode, when during the chip select is active (csb=?0?), the sda and the scl are enabled. when during the chip select is not active (csb=?1?), the sda and the scl are disabled and the internal shift register and the counter are being initialized. the 8-bit serial data on the sda is fetched at the rising edge of the scl signal (serial clock) in order of the d 7 , d 6 ?d 0 , and the fetched data is converted into the 8-bit parallel data at the rising edge of the 8th scl signal. in the 4-line serial interface mode, the transferred data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs signal. table5 rs data distinction h instruction data l display data since the serial interface operation is sensitive to external noises, the scl should be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip-selected status should be released (csb=?1?) after each of the 8-bit data transmissions. the following figure illustrates the interface timing for the 4-line serial interface operation. fig1 4-line serial interface timing d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid 1 2 3 4 5 6 7 8 csb rs sda scl
NJU6820 - 17 - (1-6) 3-line serial interface mode in the 3-line serial interface mode, when the chip select is active (csb=?0?), the sda and scl are enabled. when the chip select is not active (csb=?1?), the sda and scl are disabled and the internal shift register and counter are being initialized. 9-bit serial data on the sda is fetched at the rising edge of the scl signal in order of the rs, d 7 , d 6 ?d 0 , and the fetched data is converted into the 9-bit parallel data at the rising edge of the 9th scl signal. in the 3-line serial interface mode, data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs bit of sda data and the status of the spol, as follows. table6 spol=l spol=h rs data distinction rs data distinction l display data l instruction data h instruction data h display data since the serial interface operation is sensitive to external noises, the scl must be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip-selected status should be released (csb=?1?) after each of 9-bit data transmissions. the following figure illustrates the interface timing of the 3-line serial interface operation. fig2 3-line serial interface timing rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 csb sda scl d 0 9
NJU6820 - 18 - (2) access to the ddram when the csb signal is ?0?, the transferred data from mpu is written into the ddram or instruction register in accordance with the condition of the rs signal. when the rs signal is ?1?, the transferred data is distinguished as display data. after the ?column address? and ?row address? instructions are executed, the display data can be written into the ddram by the ?display data write? instruction. the display data is written at the rising edge of the wrb signal in the 80 series mpu mode, or at the falling edge of the e signal in the 68 series mpu mode. table6 rs data l display ram data h internal command register in the sequence of the ?display data read? operation, the transferred data from mpu is temporarily held in the internal bus-holder and then transferred to the internal data-bus. when the ?display data read? operation is executed just after the ?column address? and ?row address? instructions or ?display data write? instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated ddram address is read out from the 2nd execution. for this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read. display data write operation display data read operation fig3 note) in the16-bit data bus mode, instruction data must be 16-bit as well as the display data. n n+2 d 0 to d 15 wrb bus holder wrb n n+1 n+2 n+3 n+4 n+1 n+3 n+4 internal d 0 to d 7 (d 0 to d 15 ) rdb n n n+1 n+2 wrb address set n dummy read data read n address data read n+1 address data read n+2 address
NJU6820 - 19 - (3) access to the instruction register each instruction resisters is assigned to each address between 0 h and f h , and the content of the instruction register can be read out by the combination of the ?instruction resister address? and ?instruction resister read?. fig4 (4) 8-/16-bit data bus length for display data (in the parallel interface mode) the 8- or 16-bit data bus length for display data is determined by the ?wls? of the ?data bus length? instruction. in the 16-bit data bus mode, not only the display data but also the instruction data is required to be transferred by 16-bit data (d 15 to d 0 ). however, for the access to the instruction register, the only lower 8- bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. table8 wls data bus length mode 0 8-bit 1 16-bit (5) initial display line register the initial display line resister specifies the line address, corresponding to the initial com line, by the ?initial display line? instruction. the initial com line signifies the common driver, starting scanning the display data in the ddram, and specified by the ?initial com line? instruction. the line address, established in the initial display line resister, is preset into the line counter whenever the flm signal becomes ?1?. at the rising edge of the cl signal, the line counter is counted-up and addressed 384-bit display data corresponding to the counted-up line address, is latched into the data latch circuit. at the falling edge of the cl signal, the latched data outputs to the segment drivers. d 0 to d 7 m n wrb instruction resister address set instruction resister contents read mn rdb instruction resister address set instruction resister contents read
NJU6820 - 20 - (6) ddram mapping the ddram is capable of 1,536-bit (12-bit x 128-segment) for the column address and 40-bit for the row address. in the gradation mode, each pixel for rgb corresponds to successive 3-segment drivers, and each segment driver has 16-gradation. therefore, the lsi can drive up to 128x40 pixels in 4096-color display (16-gradation x 16-gradation x 16-gradation). in the 8-bit data bus length mode column-address 0 h 1 h fe h ff h 0 h 7bit 5bit 7bit 5bit row-address 27 h 7bit 5bit 7bit 5bit column-address abs=?1? 0 h 1 h fe h ff h 0 h 4bit 8bit 4bit 8bit row-address 27 h 4bit 8bit 4bit 8bit column-address hsw=?1? 0 h 1 h be h bf h 0 h 8bit 8bit 8bit 8bit row-address 27 h 8bit 8bit 8bit 8bit column-address c256=?1? 0 h 1 h 7e h 7f h 0 h 8bit 8bit 8bit 8bit row-address 27 h 8bit 8bit 8bit 8bit
NJU6820 - 21 - in the 16-bit data bus length mode column-address 0 h 7f h 0 h 12bit 12bit row-address 27 h 12bit 12bit fig6 in the b&w mode, only msb data from each 4-bit display data group in the ddram is used. therefore, 384 x 40 pixels in the b&w and 128 x 40 pixels in the 8-gradation are available. the range of the column address varies depending on data bus length. the range between 00 h and ff h is used in the 8-bit data bus length and the range between 00 h and 7f h is in the 16-bit data bus length. the increments for the column address and row address are set to the auto-increment mode by programming the ?axi? and ?ayi? registers of the ?increment control? instruction. in this mode, the contents of the column address and row address counters automatically increment whenever the ddram is accessed. the column address and row address counters, independent of the line counter. they are used to designate the column and row addresses for the display data transferred from mpu. on the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the flm and cl signals.
NJU6820 - 22 - - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 - - a3 - - a2 - - a1 - - a0 d7 d7 b3 d6 d6 b2 d5 d5 b1 d4 d4 b0 d3 d3 c3 d2 d2 c2 d1 d1 c1 d0 d0 c0 palette b x=01h x=7eh palette a 8bit 0x 0x01 x x x=7eh x=01h 11 x=7fh x=00h seg127 palette b palette c palette c seg0 palette a palette a seg1 palette b palette c x=00h x=7fh palette a ram map 2 (256 color mode) seg126 palette b palette c wls abs hsw ref 256 mode 1 0 1 0 0 1 1 0 a3 a2 a1 a0 b3 b2 b1 b0 c3 c2 c1 c0 palette a palette b swap palette c segax segcx ref swap segax segcx segbx segbx d3 d7 d3 d3 d7 d7 d11 d11 d15 d15 a3 d2 d6 d2 d2 d6 d6 d10 d10 d14 d14 a2 d1 d5 d1 d1 d5 d5 d9 d9 d13 d13 a1 d0 d4 d0 d0 d4 d4 d8 d8 d12 d12 a0 d7 d3 d7 d7 d2 d2 d7 d7 d10 d10 b3 d6 d2 d6 d6 d1 d1 d6 d6 d9 d9 b2 d5 d1 d5 d5 d0 d0 d5 d5 d8 d8 b1 d4 d0 d4 d4 d7 d7 d4 d4 d7 d7 b0 d3 d7 d3 d3 d4 d4 d3 d3 d4 d4 c3 d2 d6 d2 d2 d3 d3 d2 d2 d3 d3 c2 d1 d5 d1 d1 d2 d2 d1 d1 d2 d2 c1 d0 d4 d0 d0 d1 d1 d0 d0 d1 d1 c0 d7 d3 d3 d3 d7 d7 d11 d11 d15 d15 a3 d6 d2 d2 d2 d6 d6 d10 d10 d14 d14 a2 d5 d1 d1 d1 d5 d5 d9 d9 d13 d13 a1 d4 d0 d0 d0 d4 d4 d8 d8 d12 d12 a0 d3 d7 d7 d7 d2 d2 d7 d7 d10 d10 b3 d2 d6 d6 d6 d1 d1 d6 d6 d9 d9 b2 d1 d5 d5 d5 d0 d0 d5 d5 d8 d8 b1 d0 d4 d4 d4 d7 d7 d4 d4 d7 d7 b0 d7 d3 d3 d3 d4 d4 d3 d3 d4 d4 c3 d6 d2 d2 d2 d3 d3 d2 d2 d3 d3 c2 d5 d1 d1 d1 d2 d2 d1 d1 d2 d2 c1 d4 d0 d0 d0 d1 d1 d0 d0 d1 d1 c0 d3 d7 d3 d3 d7 d7 d11 d11 d15 d15 a3 d2 d6 d2 d2 d6 d6 d10 d10 d14 d14 a2 d1 d5 d1 d1 d5 d5 d9 d9 d13 d13 a1 d0 d4 d0 d0 d4 d4 d8 d8 d12 d12 a0 d7 d3 d7 d7 d2 d2 d7 d7 d10 d10 b3 d6 d2 d6 d6 d1 d1 d6 d6 d9 d9 b2 d5 d1 d5 d5 d0 d0 d5 d5 d8 d8 b1 d4 d0 d4 d4 d7 d7 d4 d4 d7 d7 b0 d3 d7 d3 d3 d4 d4 d3 d3 d4 d4 c3 d2 d6 d2 d2 d3 d3 d2 d2 d3 d3 c2 d1 d5 d1 d1 d2 d2 d1 d1 d2 d2 c1 d0 d4 d0 d0 d1 d1 d0 d0 d1 d1 c0 d7 d3 d3 d3 d7 d7 d11 d11 d15 d15 a3 d6 d2 d2 d2 d6 d6 d10 d10 d14 d14 a2 d5 d1 d1 d1 d5 d5 d9 d9 d13 d13 a1 d4 d0 d0 d0 d4 d4 d8 d8 d12 d12 a0 d3 d7 d7 d7 d2 d2 d7 d7 d10 d10 b3 d2 d6 d6 d6 d1 d1 d6 d6 d9 d9 b2 d1 d5 d5 d5 d0 d0 d5 d5 d8 d8 b1 d0 d4 d4 d4 d7 d7 d4 d4 d7 d7 b0 d7 d3 d3 d3 d4 d4 d3 d3 d4 d4 c3 d6 d2 d2 d2 d3 d3 d2 d2 d3 d3 c2 d5 d1 d1 d1 d2 d2 d1 d1 d2 d2 c1 d4 d0 d0 d0 d1 d1 d0 d0 d1 d1 c0 mode x=00h x=7fh palette a seg127 palette b palette c palette a ram map 1 seg126 palette b palette c wls abs hsw palette c seg0 palette a 10 seg1 palette b palette c 00 palette b ref 256 x 1x 0 0 x=01h x=7eh palette a x=7eh x=01h x=7fh x=00h 1 1 1 1 x x 1 0 0 0 x=7fh x=00h x=7eh x=01h x=01h x=7eh x=00h x=7fh 0 0 x x 1 1 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 8bit 16bit 0 0 1 0 0 0 0 x=beh(l) x=bfh x=bdh x=beh(h) x=bfh x=beh x=bdh x=01h(l) x=02h x=00h x=01h(h) x=02h x=01h x=00h x=feh x=ffh x=fch x=fdh x=00h x=01h x=02h x=03h x=02h x=fch x=03h x=fdh x=00h x=feh x=01h x=ffh x=02h x=03h x=00h x=01h x=feh x=ffh x=fch x=fdh x=feh x=00h x=ffh x=01h x=fch x=02h x=fdh x=03h note1) in the 256-color mode, the vacant lsb bit is filled with "1". note2) the function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). note3) the written data in the dd ram in "c256"=0 in not compatible with the data in "c256"=1. note4) in the 256-color mode, only 8-bit length mode is available, but 16-bit is not.
NJU6820 - 23 - (7) window addressing mode in addition to the above usual ddram addressing, it is possible to access some part of ddram in using the window addressing mode, in which the start and end points are designated. the start point is determined by the ?column address? and ?row address? instructions, and the end point is determined by the ?window end column address? and ?window end row address? instructions, the setting example of the window addressing is listed, as follows. 1. set win=1, axi=1 and ayi=1 by the ?increment control? instruction 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode in the window addressing mode (win=1, axi=1, ayi=1), the read-modify-write operation is available by setting ?0? to the ?aim? register of the ?increment control? instruction. and in the window addressing mode, the following start and end point must be maintained to abide a malfunction. ax (column address of start point)< ex (column address of end point)< maximum of column address ay (row address of start point)< ey (row address of end point)< maximum of row address column address (x, y) start point end point row address window display area (x, y) whole ddram area fig7 (8) reverse display on/off the ?reverse display on/off? function is used to reverse the display data without changing the contents of the ddram. table9 rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 (9) segment direction the ?segment direction? function is used to reverse the assignment for the segment drivers and column address, and it is possible to reduce the restrictions for the placement of the lsi on the lcd modules.
NJU6820 - 24 - (10) the relationship among the ddram column address, display data and segment drivers in the color mode, and 16-bit data bus mode hsw abs ref swap column address / bit / segment assign * 0 0 0 x=00 h x=7f h * 0 1 1 x=7f h x=00 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 0 0 1 x=00 h x=7f h * 0 1 0 x=7f h x=00 h d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 d 15 d 14 d 13 d 12 d 10 d 9 d 8 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign * 1 0 0 x=00 h x=7f h * 1 1 1 x=7f h x=00 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 1 0 1 x=00 h x=7f h * 1 1 0 x=7f h x=00 h d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6820 - 25 - in the color mode, and 8-bit data bus mode hsw abs ref swap column address / bit / segment assign 0 0 0 0 x=00 h x=01 h x=fe h x=ff h 0 0 1 1 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 0 0 1 x=00 h x=01 h x=fe h x=ff h 0 0 1 0 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign 0 1 0 0 x=00 h x=01 h x=fe h x=ff h 0 1 1 1 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 1 0 1 x=00 h x=01 h x=fe h x=ff h 0 1 1 0 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6820 - 26 - 1 hsw 1 hsw 1 hsw 1 hsw * abs * abs * abs * abs 1 ref 1 ref 0 ref 0 ref 1 swa p 0 swa p 1 swa p 0 swa p d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 palette b palette c segb 126 segc 1 palette c segc 1 segb 127 sega 0 palette c segc 0 segb 1 segc 0 palette a segb 0 palette b segc 0 sega 1 palette a palette b sega 0 segb 0 segc 127 column-address / bit / segment assign x=beh x=bfh x=01h column-address / bit / segment assign x=01h palette c palette a x=bdh x=beh segc 126 sega 127 palette b palette a palette b palette c palette a sega 126 palette b palette a segb 1 palette b sega 1 palette c sega 127 palette c sega 126 palette c segc 127 palette a palette a x=00h column-address / bit / segment assign segb 0 palette b sega 0 palette c x=01h segc 1 palette a segb 1 palette b x=02h sega 1 palette c segc 126 palette a palette c x=bdh segb 126 palette b sega 126 palette c x=beh segc 127 palette a sega 0 palette a x=00h column-address / bit / segment assign segb 0 palette b segc 0 palette c x=01h sega 1 palette a segb 1 palette b x=02h segc 1 palette c sega 126 palette a x=bdh segb 126 palette b segc 126 palette c x=beh sega 127 palette a x=01h segb 127 palette b x=bfh segc 127 palette c segb 127 palette b x=bfh sega 127 x=01h x=02h x=00h x=02h x=00h segb 127 palette b segc 126 palette a segb 126 x=beh x=bfh x=bdh x=beh
NJU6820 - 27 - in the color mode, 8-bit data bus mode, and c256 mode (c256=1) hsw abs ref swap column address / bit / segment assign * * 0 0 x=00 h x=7f h * * 1 1 x=7f h x=00 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * * 0 1 x=00 h x=7f h * * 1 0 x=7f h x=00 h d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 palette a palette b palette c palette a palette b palette c segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6820 - 28 - in the b&w mode, and 16-bit data bus mode hsw abs ref swap column address / bit / segment assign * 0 0 0 x=00 h x=7f h * 0 1 1 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 0 0 1 x=00 h x=7f h * 0 1 0 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign * 1 0 0 x=00 h x=7f h * 1 1 1 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign * 1 0 1 x=00 h x=7f h * 1 1 0 x=7f h x=00 h d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6820 - 29 - in the b&w mode, and 8-bit data bus mode hsw abs ref swap column address / bit / segment assign 0 0 0 0 x=00 h x=01 h x=fe h x=ff h 0 0 1 1 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 0 0 1 x=00 h x=01 h x=fe h x=ff h 0 0 1 0 x=fe h x=ff h x=00 h x=01 h d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 2 d 1 d 0 d 7 d 4 d 3 d 2 d 1 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127 hsw abs ref swap column address / bit / segment assign 0 1 0 0 x=00 h x=01 h x=fe h x=ff h 0 1 1 1 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 hsw abs ref swap column address / bit / segment assign 0 1 0 1 x=00 h x=01 h x=fe h x=ff h 0 1 1 0 x=fe h x=ff h x=00 h x=01 h d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segc 0 segb 0 sega 0 segc 127 segb 127 sega 127
NJU6820 - 30 - 1 hsw 1 hsw 1 hsw 1 hsw * abs * abs * abs * abs 1 ref 1 ref 0 ref 0 ref 1 swa p 0 swa p 1 swa p 0 swa p d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 d3 d3 d7 d7 d2 d2 d6 d6 d1 d1 d5 d5 d0 d0 d4 d4 d7 d7 d3 d3 d6 d6 d2 d2 d5 d5 d1 d1 d4 d4 d0 d0 x=beh x=bfh x=bdh x=beh column-address / bit / segment assign x=01h x=02h x=bdh x=beh x=bfh x=beh x=00h x=00h column-address / bit / segment assign x=01h x=02h x=bfh sega 0 x=bdh segc 126 x=01h x=02h x=00h x=02h x=00h column-address / bit / segment assign x=01h sega 0 column-address / bit / segment assign x=beh x=bfh x=01h x=bdh x=beh x=01h segb 0 segc 0 sega 1 segb 1 segc 1 sega 126 segb 126 segc 126 sega 127 segb 127 segc 127 segc 0 segb 0 sega 0 segc 1 segb 1 sega 1 segc 126 segb 126 sega 126 segc 127 segb 127 sega 127 segc 0 segb 0 segc 1 segb 1 sega 1 segb 126 sega 126 segc 127 segb 127 sega 127 sega 0 segb 0 segc 0 sega 1 segb 1 segc 1 sega 126 segb 126 segc 126 sega 127 segb 127 segc 127
NJU6820 - 31 - bit assignments between write and read data (in the 16-bit data bus mode) abs=0 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 15 d 14 d 13 d 12 * d 10 d 9 d 8 d 7 * * d 4 d 3 d 2 d 1 * abs=1 write data d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data * * * * d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 examples of write and read data (in the 8 bit bus mode) abs=0, hsw=0, c256=0 (address; 00, 02??fc,fe h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 1 d 2 d 1 d 0 abs=0, hsw=0, c256=0 (address; 01,03??fd,ff h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 1 1 d 4 d 3 d 2 d 1 1 abs=1, hsw=0, c256=0 (address; 00, 02??fc,fe h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data 1 1 1 1 d 3 d 2 d 1 d 0 abs=1, hsw=0, c256=0 (address; 01,03??fd,ff h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, hsw=1, c256=0 (address; 00, 01??be,bf h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 abs=0, hsw=0, c256=1 (address; 00, 01?? 7e ,7f h ) write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * : invalid data
NJU6820 - 32 - (11) gradation palette in the gradation mode, either variable or fixed gradation mode is selected by programming the ?pwm? register of the ?gradation control? instruction. pwm=0: variable gradation mode (select 16 gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) in these mode, each of the gradation palettes aj, bj and cj can select 16-gradation level out of 32- gradation level by setting 5-bit data to the ?pa? registers in the ?gradation palette j? instructions (j=0 to fh). for instance, the gradation palettes aj correspond to the segai, the bj to segbi and the cj to segci (j=0 to 15, i=0 to 127). correspondence between display data and gradation palettes table 10 (palette aj, palette bj, palette cj (j=0 to 15)) (msb) display data (lsb) gradation palette default palette value 0 0 0 0 palette 0 0 0 0 0 0 0 0 0 1 palette 1 0 0 0 1 1 0 0 1 0 palette 2 0 0 1 0 1 0 0 1 1 palette 3 0 0 1 1 1 0 1 0 0 palette 4 0 1 0 0 1 0 1 0 1 palette 5 0 1 0 1 1 0 1 1 0 palette 6 0 1 1 0 1 0 1 1 1 palette 7 0 1 1 1 1 1 0 0 0 palette 8 1 0 0 0 1 1 0 0 1 palette 9 1 0 0 1 1 1 0 1 0 palette10 1 0 1 0 1 1 0 1 1 palette11 1 0 1 1 1 1 1 0 0 palette12 1 1 0 0 1 1 1 0 1 palette13 1 1 0 1 1 1 1 1 0 palette14 1 1 1 0 1 1 1 1 1 palette15 1 1 1 1 1 gradation palette table (variable gradation mode, pwm=?0?, mon=?0?) table 11 (palette aj, palette bj, palette cj (j=0 to 15)) palette value gradation level gradation palette palette value gradation level gradation palette 0 0 0 0 0 0 palette 0(default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette 0(default)8 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 palette 1(default) 1 0 0 1 1 19/31 palette 9(default) 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette 2(default) 1 0 1 0 1 21/31 palette 10(default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 palette 3(default) 1 0 1 1 1 23/31 palette 11(default) 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 palette 4(default) 1 1 0 0 1 25/31 palette 12(default) 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 palette 5(default) 1 1 0 1 1 27/31 palette 13(default) 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 palette 6(default) 1 1 1 0 1 29/31 palette 14(default) 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 palette 7(default) 1 1 1 1 1 31/31 palette 15(default)
NJU6820 - 33 - gradation palette table (fixed gradation mode, pwm=?1?, mon=?0?) table 12 8-gradation segment drivers (msb) display data (lsb) gradation level (msb) display data (lsb) gradation level 0 0 0 * 0/7 0 0 * * 0 0 1 * 1/7 0 0 * * 0/7 0 1 0 * 2/7 0 1 * * 0 1 1 * 3/7 0 1 * * 3/7 1 0 0 * 4/7 1 0 * * 1 0 1 * 5/7 1 0 * * 5/7 1 1 0 * 6/7 1 1 * * 1 1 1 * 7/7 1 1 * * 7/7 correspondence between display data and gradation level (b&w mode, mon=?1?) table 13 (msb) display data (lsb) gradation level 0 * * * 0 1 * * * 1 *:don?t care (12) gradation control and display data (12-1) gradation mode in the graduation mode, each pixel for rgb corresponds to successive 3 segment drivers, and each segment driver provides 16-gradation pwm output by controlling 4 bit display data of the ddram. accordingly, the lsi can drive up to 128x40 pixels in 4096-color (16-gradation x 16- gradation x 16-gradation = 4-bit x 4-bit x 4-bit). in addition, the lsi can transfer the display data for the rgb by 16-bit at once or 8-bit two-times. the data assignment between gradation palettes and segment drivers varies in accordance with setting for the ?swap? and ?ref? registers of the "display control (2)" instruction. (ref, swap)=(0, 0) or (1, 1) (i=0 to 127) note) ddram column address :2n h ,2n h +1 h (ref=?0?) :fe h -2n h , ff h -(2n h +1 h ) (ref=?1?) hsw=1; 00 h to bf h , c256=1; 00 h to 7f h gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram msb lsb msb lsb msb lsb paltte aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 column address:2n h :2n+1 h ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 ( d 7 d 6 * d 5 d 4 d 3 d 2 *d 1 d 0 * ) * c256=1 segai segbi segci
NJU6820 - 34 - (ref, swap)=(0, 1) or (1, 0) note) ddram column address : 2n h ,2n h +1 h (ref=?0?) : fe h -2n h , ff h -(2n h +1 h ) (ref=?1?) hsw=1; 00 h to bf h, c256=; 00 h to 7f h in the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the ?swap? and ?ref? bit of the "display control (2)" instruction as well as the assignment in the 8-bit data bus mode. (ref, swap)=(0, 0) or (1, 1) note) ddram column address :n h (ref=?0?) :7f h - n h (ref=?1?) gradation palette j =0 to 15 dis p la y data from mpu gradation control circuit display data in ddram segai segbi segci column address:2n h :2n+1 h ( i=0 to 127 ) lsb msb lsb msb lsb msb palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 7 d 6 d 4 d 5 d 2 d 1 d 0 d 7 d 4 d 3 d 1 d 2 ( d 7 d 6 * d 5 d 4 d 3 d 2 * d 1 d 0 * ) * c256=1 ( d 3 d 2 d 0 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 ( d 7 d 6 d 4 d 5 d 3 d 2 d 1 d 0 d 7 d 6 d 4 ) d 5 hsw=1 segai segbi segci (i=0 to 127) msb lsb msb lsb msb gradation palette j =0 to 15 display data from mpu gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 column address ; n h
NJU6820 - 35 - gradation palette j =0 to 15 (i=0 to 127) dis p la y data from mpu gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 d 1 5 d 14 d 12 d 1 3 d 1 0 d 9 d 8 d 7 d 4 d 3 d 1 d 2 column address ; n h ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 (ref, swap)=(0, 1) or (1, 0) note) ddram column address :n h (ref=?0?) :7f h -n h (ref=?1?)
NJU6820 - 36 - (12-2) b&w mode (mon=?1?) in the b&w mode, 3 bits of the msb data are used in both of the 16-bit and 8-bit data bus modes. in the 16-bit data bus mode (similarly 8-bit data bus access) (ref, swap)=(0, 0) or (1, 1) note) ddram column address : n h (ref=?0?) : 7f h -n h (ref=?1?) (ref, swap)=(0, 1) or (1, 0) note ) ddram column address : n h (ref=?0?) : 7f h -n h (ref=?1?) segai segbi segci msb lsb msb lsb msb gradation palette j =0 to 15 (i=0 to 127) dis p la y data in ddram gradation control circuit display data in ddram lsb palette aj palette bj palette cj 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 10 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1 gradation palette j =0 to 15 (i=0 to 127) dis p la y data in ddram gradation control circuit display data in ddram lsb msb lsb msb lsb msb segai segbi segci palette aj palette bj palette cj 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 column address; n h d 15 d 14 d 12 d 13 d 10 d 9 d 8 d 7 d 4 d 3 d 1 d 2 ( d 11 d 1 0 d 8 d 9 d 7 d 6 d 5 d 4 d 3 d 2 d 0 ) d 1 a bs=1
NJU6820 - 37 - (13) display timing generator the display-timing generator creates the timing pulses such as the cl, the flm, the fr and the clk by dividing the oscillation frequency oscillate an external or internal resister mode. the each of timing pulses is outputted through the each output terminals by ?son? = 1. (14) lcd line clock (cl) the lcd line clock (cl) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. at the rising edge of the cl signal, the line counter is counted-up and the 384-bit display data, corresponding to this line address, is latched into the data latch circuit. and at the falling edge of the cl signal, this latched data output on the segment drivers. read out timing of the display data, from ddram to the latch circuits is completely independent of the access timing to the mpu. for this reason, the mpu can access to the lsi regardless of an internal operation. (15) lcd alternate signal (fr) and lcd synchronous signal (flm) the fr and flm signals are created from the cl signal. the fr signal is used to alternate the crystal polarization on a lcd panel. it is programmed that the fr signal is toggle on every frame in the default setting or once every n lines in the n-line inversion mode. the flm signal is used to indicate a start line of a new display frame. it presets an initial display line address of the line counter when the flm signal becomes ?1?. (16) data latch circuit the data latch circuit is used temporarily store the display data that will output to the segment drivers. the display data in this circuit is updated in synchronization of the cl signal. the ?all pixels on/off?, ?display on/off? and ?reverse display on/off? instructions change the display data in this circuit but do not change the display data of the ddram. (17) common and segment drivers the lsi includes 384-segment drivers and 40-common drivers. the common drivers generate the lcd driving waveforms composed of the v lcd , v 1 , v 4 and v ss in accordance with the fr signal and scanning data. the segment drivers generate waveforms composed of the v lcd , v 2 , v 3 and v ss in accordance with the fr signal and display data.
NJU6820 - 38 - lcd driving waveforms (in the b&w mode, reverse display off, 1/41 duty) fig 8 com 1 com 0 seg 1 seg 0 seg 2 com 1 com 0 v 1 v 2 cl v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss seg 1 seg 0 v lcd v 3 v 4 v ss fr flm 41 1 2 4 35 41 12 4 35 41 1
NJU6820 - 39 - (18) oscillator the oscillator generates internal clocks for the display timing and the voltage booster. since the lsi has internal capacitor (c) and resistor (r) for the oscillation, external capacitor and resistor are not usually required. however, in case that an external resistor is used, the resister is connected between the osc1 and osc2 terminals. the external resistor becomes enabled by setting ?1? to the ?cks? register of ?data bus length? instruction. when the internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the osc1 terminal. in addition, the feed back resister for the oscillation is varied by programming the ?rf? register of the ?frequency control? instruction, so that it is possible to optimize the frame frequency for a lcd panel. setting examples of the mon (b&w /gradation) and the pwm (variable gradation /fixed gradation) are described, as follows. (18-1) internal oscillation mode (cks=0) symbol mon pwm display mode f 1 0 0 variable gradation mode f 2 0 1 fixed gradation mode f 3 1 * b&w mode *: don?t care (18-2) external resistor oscillation mode(cks=1) the internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (18-3) external clock input mode (cks=1) the external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?mon? and ?pwm? registers must be set as well. (19) power supply circuits the internal power supply circuits are composed of the voltage booster, the electrical variable resister (evr), the voltage regulator, reference voltage generator and the voltage followers. the condition of the power supply circuits is arranged by programming the ?dcon? and ?ampon? registers on the ?power control? instruction. for this arrangement, same parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. table 14 dcon ampon voltage booster voltage followers voltage regulator evr external voltage note 0 0 disable disable v out , v lcd , v 1 , v 2 , v 3 , v 4 1, 3 0 1 disable enable v out 2, 3 1 1 enable enable ? ? note1) the internal power circuits are not used. the external v out is required and the c1+, c1-, c2+, c2-, c3+, c3-, c4+, c4-, v out , v ref , v reg and v ee terminals must be open. note2) the internal power circuits except the voltage booster are used. the external v out is required and the c1+, c1-, c2+, c2-, c3+, c3-, c4+, c4- and v ee terminals must be open. the reference voltage is required to v ref terminal. note3) the relation among the voltages should be maintained as follows. v out v lcd v 1 v 2 v 3 v 4 v ss
NJU6820 - 40 - (20) voltage booster the voltage booster generates maximum 5x voltage of the v ee level. it is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, and 5x by the ?boost level select? instruction. the boosted voltage v out must not exceed beyond the value of 18.0v, otherwise the voltage stress may cause a permanent damage to the lsi. boosted voltages capacitor connections for the voltage booster 5-time boost 4-time boost 3-time boost 2-time boost fig 9 3-time boost 5-time boost v ss =0v v ee =3v v out =9v v out =15v v ss =0v v ee =3v c1+ c1- c2+ c2- c3+ c3- c4+ c4- v out v ss + + + + + c1+ c1- c2+ c2- c3+ c3- c4+ c4- v out v ss + + + + c1+ c1- c2+ c2- c3+ c3- c4+ c4- v out v ss + + + c1+ c1- c2+ c2- c3+ c3- c4+ c4- v out v ss + +
NJU6820 - 41 - (21) reference voltage generator the reference voltage generator is used to produce the reference voltage (v ba ), which is output from the v ba terminal and should be input to the v ref terminal. v ba = v ee x 0.9 (22) voltage regulator the voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain the reference voltage (v ref ) and to create the regulated voltage (v reg ). the v reg is used as an input voltage to the evr circuits, which is programmed by the ?vu? register of the ?boost level? instruction. v reg = v ref x n (n: register value for the boost level) (23) electrical variable resister (evr) the evr, variable within 128-step, and is used to fine-tune the lcd driving voltage (v lcd ) by programming the ?dv? register in the ?evr control? instruction, so that it is possible to optimize the contrast level for a lcd panels. v lcd = 0.5 x v reg + m (v reg - 0.5 x v reg ) / 127 (m: register value for the evr) (24) lcd driving voltage generation circuit lcd driving voltage generation circuit generates the v lcd voltage levels as v lcd , v 1 , v 2 , v 3 and v 4 with internal e.v.r and the bleeder resistors. the bias ratio of lcd driving voltage can be selected out of 1/4, 1/5, 1/6, 1/7 and 1/8. in using the internal power supply, the capacitors ca 2 must be connected to the v lcd , v 1 , v 2 , v 3 and v 4 terminals, and the ca 2 value must be determined by the evaluation with actual lcd modules. in using the external power supply, the external lcd driving voltages such as the v lcd , v 1 , v 2 , v 3 and v 4 are supplied and the internal power supply circuits must be set to ?off? by dcon = ampon = "0". in this mode, voltage booster terminals such as c1+, c1-, c2+, c2-, c3+, c3-, c4+, c4-, v ee , v ref and v reg must be opened. in case that the voltage booster is not used but only some parts of internal power supply circuits (voltage followers, voltage regulator and evr) are used, the c1+, c1-, c2+, c2-, c3+, c3-, c4+ and c4- terminals must be opened. and, the external power supply is input to the v out terminal, and the reference voltage to the v ref terminal. the capacitor ca 3 must connect to the v reg terminal for voltage stabilization.
NJU6820 - 42 - connections of the capacitor for the voltage booster fig 10 fig11 reference values ca 1 1.0 to 4.7uf ca 2 1.0 to 2.2uf ca 3 0.1uf note) b grade capacitors are required. using only external power supply circuits using all of the internal power supply circuits (5-time boost) v dd v ee v ba v ref v reg c1- c1+ c2- c2+ c3- c3+ c4- c4+ v out v lcd v 1 v 2 v 3 v 4 v dd v lcd v 1 v 2 v 3 v 4 external power circuit NJU6820 v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 v dd v ee v ba v ref v reg c1- c1+ c2- c2+ c3- c3+ c4- c4+ v out v lcd ca 2 ca 2 ca 2 ca 2 NJU6820 ca 3 v ss
NJU6820 - 43 - fig 12 fig 13 reference value ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note) b grade capacitors are required. using internal power supply circuits without the reference voltage generator(1) (5-time boost) using internal power supply circuit without the reference voltage generator(2) (5-time boost) v dd v ee v ba v ref v reg c1- c1+ c2- c2+ c3- c3+ c4- c4+ v out v lcd v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 NJU6820 v dd v ee v ba v ref v reg c1- c1+ c2- c2+ c3- c3+ c4- c4+ v out v lcd v 1 v 2 v 3 v 4 v dd ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 NJU6820 thermistor
NJU6820 - 44 - fig 14 reference value ca 1 1.0 to 4.7 f ca 2 1.0 to 2.2 f ca 3 0.1 f note) b grade capacitors are required. using internal power supply circuits without the voltage booster v dd ca 3 v ss v ss ca 2 ca 2 ca 2 external power circuit ca 3 v ss v dd v ee v ba v ref v reg c1- c1+ c2- c2+ c3- c3+ c4- c4+ v out v lcd v 1 v 2 v 3 v 4 ca 2 ca 2 NJU6820
NJU6820 - 45 - (25) partial display function the partial display function is used to partially specify some parts of display area on lcd panels. by using this function, lcd modules can work in lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. it is usually used to display a time and calendar, and is also used to optimize the lsi condition in accordance with the display size. it can be programmed to select the duty cycle ratio (1/5, 1/9, 1/13, 1/17, 1/21, 1/25, 1/29, 1/33, 1/37, 1/41 in case ?dse? is ?0?), the lcd bias ratio, the boost level and the evr value by the instructions. partial display image normal display partial display partial display sequence - boost level - evr value - lcd bias ratio - duty cycle ratio - initial display line - initial com line - other instructions njrc lcd driver low power and low voltage lcd driver optional status display off (on/off=?0?) internal power supply off (dcon=?0?, ampon=?0?) wait setting for lcd driving voltage-related functions setting for display-related functions internal power supply on (dcon=?1?, ampon=?1?) wait display on (on/off =?1?) partial display status
NJU6820 - 46 - (26) discharge circuit discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and v lcd terminals. this circuit is activated by setting ?0? to the ?dis? register of the ?discharge? instruction or by setting ?resb? terminal to ?0? level. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. (27) reset circuit the reset circuit initializes the lsi into the following default status. it is activated by setting the resb terminal to ?0?. the resb terminal is usually required to connect to mpu reset terminal in order that the lsi can be initialized at the same timing of the mpu. default status 1. ddram display data :undefined 2. column address :(00) h 3. row address :(00) h 4. initial display line :(0) h (1st line) 5. display on/off :off 6. reverse display on/off :off (normal) 7. duty cycle ratio :1/41 duty(dse=0) 8. n-line inversion on/off :off 9. com scan direction :com 0 com 39 10. increment mode :off 11. reverse seg direction :off (normal) 12. swap mode :off (normal) 13. evr value :(0, 0, 0, 0, 0, 0, 0) 14. internal power supply :off 15. display mode :gradation display mode 16. lcd bias ratio :1/8 bias 17. gradation palette 0 :(0, 0, 0, 0, 0) 18. gradation palette 1 :(0, 0, 0, 1, 1) 19. gradation palette 2 :(0, 0, 1, 0, 1) 20. gradation palette 3 :(0, 0, 1, 1, 1) 21. gradation palette 4 :(0, 1, 0, 0, 1) 22. gradation palette 5 :(0, 1, 0, 1, 1) 23. gradation palette 6 :(0, 1, 1, 0, 1) 24. gradation palette 7 :(0, 1, 1, 1, 1) 25. gradation palette 8 :(1, 0, 0, 0, 1) 26. gradation palette 9 :(1, 0, 0, 1, 1) 27. gradation palette 10 :(1, 0, 1, 0, 1) 28. gradation palette 11 :(1, 0, 1, 1, 1) 29. gradation palette 12 :(1, 1, 0, 0, 1) 30. gradation palette 13 :(1, 1, 0, 1, 1) 31. gradation palette 14 :(1, 1, 1, 0, 1) 32. gradation palette 15 :(1, 1, 1, 1, 1) 33. gradation mode control :variable gradation mode 34. data bus length :8-bit data bus length 35. discharge circuit :(dis/dis2) : ?0?
NJU6820 - 47 - (28) power supply on/off sequences the following paragraphs describe power supply on/off sequences, which are to protect the lsi from over current. (28-1) using an external power supply power supply on sequence logic voltage (v dd ) must be always input first, and next the lcd driving voltages (v 1 to v 4 and v lcd ) are turned on. in using the external v out , the v dd must be input first, next the reset operation must be performed, and finally the v out can be input. power supply off sequence either the reset operation, cutting off the v 1 to v 4 and v lcd from the lsi by the resb terminal or the ?power control? instruction must be performed first, and next the v dd is turned off. it is recommended that a series-resister between 50 ? and 100 ? is added on the v lcd line (or v out line in using only the external v out voltage) in order to protect the lsi from the over current. (28-2) using the internal power supply circuits power supply on sequence the v dd must be input first, next the reset operation must be performed, and finally the v 1 to v 4 and v lcd can be turned on by setting ?1? to the ?dcon? and ?ampon? registers of the ?power control? instruction. power supply off sequence either the reset operation by the resb terminal or the ?power control? instruction must be performed first, and next the input voltage for the voltage booster (v ee ) and the v dd can be turned off. if the v ee is supplied from different power sources for v dd , the v ee is turned off first, and next the v dd is turned off.
NJU6820 - 48 - (29) referential instruction sequences (29-1) initialization in using the internal power supply circuits - evr value - lcd bias ratio - power control (dcon=?1?, ampon=?1?) (29-2) display data writing - initial display line - increment mode - column address - row address (29-3) power off - all com/seg output v ss level. v dd , v ee power on wait for power-on stabilization reset input wait setting for lcd driving voltage-related functions end of initialization end of initialization setting for display-related functions display on (on/off =?1?) display data write optional status power save or reset operation v ee , v dd power off wait discharge on
NJU6820 - 49 - (30) instruction table instruction table (1) code (80 series mpu i/f) code instructions csb rs rdb w rb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions display data write 0 0 1 0 0/1 0/1 0/1 write data write display data to ddram display data read 0 0 0 1 0/1 0/1 0/1 read data read display data from ddram column address (lower) [0 h ] 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 ddram column address column address (upper) [1 h ] 0 1 1 0 0 0 0 0 0 0 1 ax7 ax6 ax5 ax4 ddram column address row address (lower) [2 h ] 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 ddram row address row address (upper) [3 h ] 0 1 1 0 0 0 0 0 0 1 1 * * ay5 ay4 ddram row address initial display line (lower) [4 h ] 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 row address for an initial com line (scan start line) initial display line (upper) [5 h ] 0 1 1 0 0 0 0 0 1 0 1 * * la5 la4 row address for an initial com line (scan start line) n-line inversion (lower) [6 h ] 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 the number of n-line inversion n-line inversion (upper) [7 h ] 0 1 1 0 0 0 0 0 1 1 1 * * n5 n4 the number of n-line inversion display control (1) [8 h ] 0 1 1 0 0 0 0 1 0 0 0 shift mon all on on/ off shift: common direction mon: gradation or b/w display mode allon: all pixels on/off on/off: display on/off display control (2) [9 h ] 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref rev: reverse display on/off nlin: n-line inversion on/off, swap: swap mode on/off ref: segment direction increment control [a h ] 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi win: window addressing mode on/off aim: read-modify-write on/off ayi: row auto-increment mode on/off axi: column auto-increment mode on/off power control [b h ] 0 1 1 0 0 0 0 1 0 1 1 amp on halt dc on acl ampon: voltage followers on/off halt: power save on/off dcon: voltage booster on/off acl: reset duty cycle ratio [c h ] 0 1 1 0 0 0 0 1 1 0 0 ds3 ds2 ds1 ds0 sets lcd duty cycle ratio boost level [d h ] 0 1 1 0 0 0 0 1 1 0 1 * vu2 vu1 vu0 sets boost level lcd bias ratio [e h ] 0 1 1 0 0 0 0 1 1 1 0 * b2 b1 b0 sets lcd bias ratio re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6820 - 50 - instruction table (2) code (80 series mpu i/f) code instructions csb rs rdb w rb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a0/a8 (lower) [0 h ] 0 1 1 0 0 0 1 0 0 0 0 pa03/ pa83 pa02/ pa82 pa01/ pa81 pa00/ pa80 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a0/a8 (upper) [1 h ] 0 1 1 0 0 0 1 0 0 0 1 * * * pa04/ pa84 sets palette values to gradation palette a0(ps=0)/a8(ps=1) gradation palette a1/a9 (lower) [2 h ] 0 1 1 0 0 0 1 0 0 1 0 pa13/ pa93 pa12/ pa92 pa11/ pa91 pa10/ pa90 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a1/a9 (upper) [3 h ] 0 1 1 0 0 0 1 0 0 1 1 * * * pa14/ pa94 sets palette values to gradation palette a1(ps=0)/a9(ps=1) gradation palette a2/a10 (lower) [4 h ] 0 1 1 0 0 0 1 0 1 0 0 pa23/ pa103 pa22/ pa102 pa21/ pa101 pa20/ pa100 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a2/a10 (upper) [5 h ] 0 1 1 0 0 0 1 0 1 0 1 * * * pa24/ pa104 sets palette values to gradation palette a2(ps=0)/a10(ps=1) gradation palette a3/a11 (lower) [6 h ] 0 1 1 0 0 0 1 0 1 1 0 pa33/ pa113 pa32/ pa112 pa31/ pa111 pa30/ pa110 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a3/a11 (upper) [7 h ] 0 1 1 0 0 0 1 0 1 1 1 * * * pa34/ pa114 sets palette values to gradation palette a3(ps=0)/a11(ps=1) gradation palette a4/a12 (lower) [8 h ] 0 1 1 0 0 0 1 1 0 0 0 pa43/ pa123 pa42/ pa122 pa41/ pa121 pa40/ pa120 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a4/a12 (upper) [9 h ] 0 1 1 0 0 0 1 1 0 0 1 * * * pa44/ pa124 sets palette values to gradation palette a4(ps=0)/a12(ps=1) gradation palette a5/a13 (lower) [a h ] 0 1 1 0 0 0 1 1 0 1 0 pa53/ pa133 pa52/ pa132 pa51/ pa131 pa50/ pa130 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a5/a13 (upper) [b h ] 0 1 1 0 0 0 1 1 0 1 1 * * * pa54/ pa134 sets palette values to gradation palette a5(ps=0)/a13(ps=1) gradation palette a6/a14 (lower) [c h ] 0 1 1 0 0 0 1 1 1 0 0 pa63/ pa143 pa62/ pa142 pa61/ pa141 pa60/ pa140 sets palette values to gradation palette a6(ps=0)/a14(ps=1) gradation palette a6/a14 (upper) [d h ] 0 1 1 0 0 0 1 1 1 0 1 * * * pa64/ pa144 sets palette values to gradation palette a6(ps=0)/a14(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6820 - 51 - instruction table (3) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a7/a15 (lower) [0 h ] 0 1 1 0 0 1 0 0 0 0 0 pa73/ pa153 pa72/ pa152 pa71/ pa151 pa70/ pa150 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette a7/a15 (upper) [1 h ] 0 1 1 0 0 1 0 0 0 0 1 * * * pa74/ pa154 sets palette values to gradation palette a7(ps=0)/a15(ps=1) gradation palette b0/b8 (lower) [2 h ] 0 1 1 0 0 1 0 0 0 1 0 pb03/ pb83 pb02/ pb82 pb01/ pb81 pb00/ pb80 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b0/b8 (upper) [3 h ] 0 1 1 0 0 1 0 0 0 1 1 * * * pb04/ pb84 sets palette values to gradation palette b0(ps=0)/b8(ps=1) gradation palette b1/b9 (lower) [4 h ] 0 1 1 0 0 1 0 0 1 0 0 pb13/ pb93 pb12/ pb92 pb11/ pb91 pb10/ pb90 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b1/b9 (upper) [5 h ] 0 1 1 0 0 1 0 0 1 0 1 * * * pb14/ pb94 sets palette values to gradation palette b1(ps=0)/b9(ps=1) gradation palette b2/b10 (lower) [6 h ] 0 1 1 0 0 1 0 0 1 1 0 pb23/ pb103 pb22/ pb102 pb21/ pb101 pb20/ pb100 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b2/b10 (upper) [7 h ] 0 1 1 0 0 1 0 0 1 1 1 * * * pb24/ pb104 sets palette values to gradation palette b2(ps=0)/b10(ps=1) gradation palette b3/b11 (lower) [8 h ] 0 1 1 0 0 1 0 1 0 0 0 pb33/ pb113 pb32/ pb112 pb31/ pb111 pb30/ pb110 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b3/b11 (upper) [9 h ] 0 1 1 0 0 1 0 1 0 0 1 * * * pb34/ pb114 sets palette values to gradation palette b3(ps=0)/b11(ps=1) gradation palette b4/b12 (lower) [a h ] 0 1 1 0 0 1 0 1 0 1 0 pb43/ pb123 pb42/ pb122 pb41/ pb121 pb40/ pb120 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b4/b12 (upper) [b h ] 0 1 1 0 0 1 0 1 0 1 1 * * * pb44/ pb124 sets palette values to gradation palette b4(ps=0)/b12(ps=1) gradation palette b5/b13 (lower) [c h ] 0 1 1 0 0 1 0 1 1 0 0 pb53/ pb133 pb52/ pb132 pb51/ pb131 pb50/ pb130 sets palette values to gradation palette b5(ps=0)/b13(ps=1) gradation palette b5/b13 (upper) [d h ] 0 1 1 0 0 1 0 1 1 0 1 * * * pb54/ pb134 sets palette values to gradation palette b5(ps=0)/b13(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6820 - 52 - instruction table (4) code (80 series mpu i/f) code instructions csb rs rdb w rb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette b6/b14 (lower) [0 h ] 0 1 1 0 0 1 1 0 0 0 0 pb63/ pb143 pb62/ pb142 pb61/ pb141 pb60/ pb140 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b6/b14 (upper) [1 h ] 0 1 1 0 0 1 1 0 0 0 1 * * * pb64/ pb144 sets palette values to gradation palette b6(ps=0)/b14(ps=1) gradation palette b7/b15 (lower) [2 h ] 0 1 1 0 0 1 1 0 0 1 0 pb73/ pb153 pb72/ pb152 pb71/ pb151 pb70/ pb150 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette b7/b15 (upper) [3 h ] 0 1 1 0 0 1 1 0 0 1 1 * * * pb74/ pb154 sets palette values to gradation palette b7(ps=0)/b15(ps=1) gradation palette c0/c8 (lower) [4 h ] 0 1 1 0 0 1 1 0 1 0 0 pc03/ pc83 pc02/ pc82 pc01/ pc81 pc00/ pc80 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c0/c8 (upper) [5 h ] 0 1 1 0 0 1 1 0 1 0 1 * * * pc04/ pc84 sets palette values to gradation palette c0(ps=0)/c8(ps=1) gradation palette c1/c9 (lower) [6 h ] 0 1 1 0 0 1 1 0 1 1 0 pc13/ pc93 pc12/ pc92 pc11/ pc91 pc10/ pc90 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c1/c9 (upper) [7 h ] 0 1 1 0 0 1 1 0 1 1 1 * * * pc14/ pc94 sets palette values to gradation palette c1(ps=0)/c9(ps=1) gradation palette c2/c10 (lower) [8 h ] 0 1 1 0 0 1 1 1 0 0 0 pc23/ pc103 pc22/ pc102 pc21/ pc101 pc20/ pc100 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c2/c10 (upper) [9 h ] 0 1 1 0 0 1 1 1 0 0 1 * * * pc24/ pc104 sets palette values to gradation palette c2(ps=0)/c10(ps=1) gradation palette c3/c11 (lower) [a h ] 0 1 1 0 0 1 1 1 0 1 0 pc33/ pc113 pc32/ pc112 pc31/ pc111 pc30/ pc110 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c3/c11 (upper) [b h ] 0 1 1 0 0 1 1 1 0 1 1 * * * pc34/ pc114 sets palette values to gradation palette c3(ps=0)/c11(ps=1) gradation palette c4/c12 (lower) [c h ] 0 1 1 0 0 1 1 1 1 0 0 pc43/ pc123 pc42/ pc122 pc41/ pc121 pc40/ pc120 sets palette values to gradation palette c4(ps=0)/c12(ps=1) gradation palette c4/c12 (upper) [d h ] 0 1 1 0 0 1 1 1 1 0 1 * * * pc44/ pc124 sets palette values to gradation palette c4(ps=0)/c12(ps=1) re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag set note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6820 - 53 - instruction table (5) code (80 series mpu i/f) code instructions csb rs rdb w rb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette c5/c13 (lower) [0 h ] 0 1 1 0 1 0 0 0 0 0 0 pc53/ pc133 pc52/ pc132 pc51/ pc131 pc50/ pc130 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c5/c13 (upper) [1 h ] 0 1 1 0 1 0 0 0 0 0 1 * * * pc54/ pc134 sets palette values to gradation palette c5(ps=0)/c13(ps=1) gradation palette c6/c14 (lower) [2 h ] 0 1 1 0 1 0 0 0 0 1 0 pc63/p c143 pc62/ pc142 pc61/ pc141 pc60/ pc140 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c6/c14 (upper) [3 h ] 0 1 1 0 1 0 0 0 0 1 1 * * * pc64/ pc144 sets palette values to gradation palette c6(ps=0)/c14(ps=1) gradation palette c7/c15 (lower) [4 h ] 0 1 1 0 1 0 0 0 1 0 0 pc73/ pc153 pc72/ pc152 pc71/ pc151 pc70/ pc150 sets palette values to gradation palette c7(ps=0)/c15(ps=1) gradation palette c7/c15 (upper) [5 h ] 0 1 1 0 1 0 0 0 1 0 1 * * * pc74/ pc154 sets palette values to gradation palette c7(ps=0)/c15(ps=1) initial com line [6 h ] 0 1 1 0 1 0 0 0 1 1 0 sc3 sc2 sc1 sc0 sets scan-starting common driver display control signal/ duty select [7 h ] 0 1 1 0 1 0 0 0 1 1 1 * * dse son son : display clock on/off dse : duty-1 on/off gradation mode control [8 h ] 0 1 1 0 1 0 0 1 0 0 0 pwm c256 * * pwm : variable/fixed gradation mode c256 : 256-color mode on/off data bus length [9 h ] 0 1 1 0 1 0 0 1 0 0 1 hsw abs cks wls hsw : high speed access on/off abs : abs m ode on/off cks : internal/external oscilation wls : display data length evr control (lower) [a h ] 0 1 1 0 1 0 0 1 0 1 0 dv3 dv2 dv1 dv0 sets evr level (lower bit) evr control (upper) [b h ] 0 1 1 0 1 0 0 1 0 1 1 * dv6 dv5 dv4 sets evr level (upper bit) frequency control [d h ] 0 1 1 0 1 0 0 1 1 0 1 * rf2 rf1 rf0 oscillation frequency discharge on/off [e h ] 0 1 1 0 1 0 0 1 1 1 0 * * dis2 dis discharge the electric charge in capacitors on v 1 to v 4 and v lcd re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag instruction register address [c h ] 0 1 1 0 1 0 0 1 1 0 0 reading address sets instruction register address instruction register read 0 1 0 1 0/1 0/1 0/1 * * * * read data read out instruction register data note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. note 4) cks=0: internal oscillation mode (default) cks=1: external oscillation mode
NJU6820 - 54 - instruction table (6) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions window end column address (lower) [0 h ] 0 1 1 0 1 0 1 0 0 0 0 ex3 ex2 ex1 ex0 sets column address for end point window end column address (upper) [1 h ] 0 1 1 0 1 0 1 0 0 0 1 ex7 ex6 ex5 ex4 sets column address for end point window end row address (lower) [2 h ] 0 1 1 0 1 0 1 0 0 1 0 ey3 ey2 ey1 ey0 sets row address for end point window end row address (upper) [3 h ] 0 1 1 0 1 0 1 0 0 1 1 * * ey5 ey4 sets row address for end point initial reverse line (lower) [4 h ] 0 1 1 0 1 0 1 0 1 0 0 ls3 ls2 ls1 ls0 sets address for reverse line initial reverse line (upper) [5 h ] 0 1 1 0 1 0 1 0 1 0 1 * * ls5 ls4 sets address for reverse line last reverse line (lower) [6 h ] 0 1 1 0 1 0 1 0 1 1 0 le3 le2 le1 le0 sets address for reverse line last reverse line (upper) [7 h ] 0 1 1 0 1 0 1 0 1 1 1 * * le5 le4 sets address for reverse line reverse line display on/off [8 h ] 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev bt : blink type setting lrev : reverse line display on/off gradation palette setting control / icon seg address set [9 h ] 0 1 1 0 1 0 1 1 0 0 1 * * * ps ps : gradation setting pwm control [a h ] 0 1 1 0 1 0 1 1 0 1 0 pwm s pwm a pwm b pwm c sets pwm mode re register [f h ] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0 re flag note 1) * : don?t care. note 2) [ n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set.
NJU6820 - 55 - (31) instruction descriptions this chapter provides detail descriptions and instruction registers. nonexistent instruction codes must not be set into the lsi. (31-1) display data write the ?display data write? instruction is used to write 8-bit display data into the ddram. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0/1 0/1 0/1 display data (31-2) display data read the ?display data read? instruction is used to read out 8-bit display data from the ddram, where the column address and row address must be specified beforehand by the ?column address? and ?row address? instructions. the dummy read is required just after the ?column address? and ?row address? instructions. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0/1 0/1 0/1 display data (31-3) column address the ?column address? instruction is used to specify the column address for the display data?s reading and writing operations. it requires dual bytes for lower 4-bit and upper 4-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 0 ax 3 ax 2 ax 1 ax 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 1 ax 7 ax 6 ax 5 ax 4 (31-4) row address the ?row address? instruction is used to specify the row address for the display data read and write operations. it requires dual bytes for lower 4-bit and upper 2-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for upper 2-bit. the row address is specified in between 00 h and 27 h . the setting for nonexistent row address between 28 h and 3f h is prohibited. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 0 ay 3 ay 2 ay 1 ay 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 1 * * ay 5 ay 4
NJU6820 - 56 - (31-5) initial display line the ?initial display line? instruction is used to specify the line address corresponding to the initial com line. the initial com line specified by the ?initial com line? instruction and indicates the common driver that starts scanning data. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 0 la 3 la 2 la 1 la 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 1 * * la 5 la 4 la 5 la 4 la 3 la 2 la 1 la 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 0 1 1 1 39 (31-6) n-line inversion the ?n-line inversion? instruction is used to control the alternate rates of the liquid crystal direction. it is programmed to select the n value between 2 and 39, and the fr signal toggles once every n lines by setting ?1? into the ?nlin? register of the ?display control (2)? instruction. when the n-line inversion is disabled by setting ?0? into the ?nlin? register, the fr signal toggles by the frame. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 1 * * n5 n4 la 5 la 4 la 3 la 2 la 1 la 0 n value 0 0 0 0 0 0 inhibited* 0 0 0 0 0 1 2 : : : : 1 0 0 1 1 0 39
NJU6820 - 57 - n-line inversion timing (1/41 duty cycle ratio) n-line inversion off n-line inversion on (31-7) display control (1) the ?display control (1)? instruction is used to control display conditions by setting the ?display on/off?, ?all pixels on/off?, display mode? and ?common direction? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 0 shift mon allon on/off on/off register on/off=0 : display off (all com/seg output vss level.) on/off=1 : display on all on register the ?all pixels on/off? register is used to turn on all pixels without changing display data of the ddram. the setting for the ?all pixels on/off? register has a priority over the ?reverse display on/off? register. allon=0 : normal allon=1 : all pixels turn on. mon register mon=0 : gradation mode mon=1 : b&w mode shift register shift=0 : com 0 com 39 shift=1 : com 39 com 0 cl flm fr 2nd line 41th line 1st line 3rd line 1st line 40th line cl fr n-line control 2nd line 1st line 1st line 3rd line 2nd line n line
NJU6820 - 58 - (31-8) display control (2) the ?display control (2)? instruction is used to control display conditions by setting ?segment direction?, ?swap mode on/off?, ?n-line inversion on/off? and ?reverse display on/off? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref ref register the ?ref? register is used to reverse the assignment between segment drivers and column address, and it is possible to reduce restrictions for placement of the lsi on the lcd modules. for more information, see (10) ?the relation among the ddram column address, display data and segment drivers?. swap register the ?swap? register is used to reverse the arrangement of the display data in the ddram. swap=0 : swap mode off (normal) swap=1 : swap mode on swap=?0? swap=?1? write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ram data d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 nlin register the ?nlin? is used to enable or disable the n-line inversion. nlin=0 : n-line inversion off (the fr signal toggles by the flame.) nlin=1 : n-line inversion on (the fr signal toggles once every n frames.) rev register the ?rev? register is used to enable or disable the reverse display mode that reverses the polarity of the display data without changing the display data of the ddram. rev=0 : reverse display mode off rev=1 : reverse display mode on rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0
NJU6820 - 59 - (31-9) increment control the ?increment control? instruction is used for the increment mode. in using the auto-increment mode, ddram address automatically increments (+1) whenever the ddram is accessed by the ?display data write? or ?display data read? instruction. therefore, once ?display data write? or ?display data read? instruction is established, it is possible to continuously access to the ddram without the ?column address? and ?row address? instructions. the settings for the ?aim?, ?axi? and ?ayi? registers are listed in the following tables. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi aim, ayi and axi registers aim increment mode note 0 auto-increment for both of the display data read and write operations 1 1 auto-increment for the display write operation (read modify write) 2 note 1) it is effective for usual operations accessing successive addresses. note 2) it is effective for the read-modify-write operation. ayi axi increment mode note 0 0 no auto-increment 1 0 1 auto-increment for the column address 2 1 0 auto-increment for the row address 3 1 1 auto-increment for the column address and row address 4 note 1) auto-increment is disabled regardless of the ?aim? register. note 2) auto-increment is of the column address is enabled in accordance with the ?aim? register. note 3) auto-increment of the row address is enabled in accordance with the ?aim? register. note 4) auto-increment of the column address and the row address are enabled. the row address increments whenever the column address reaches to the max h . 00 h max h 27 h 00 h max h 00 h 7f h 00 h column address row address max h in the 8-bit data bus mode : ff h max h in the 16-bit data bus mode : 7f h max h in the 8-bit data bus mode : ff h max h in the 16-bit data bus mode : 7f h
NJU6820 - 60 - win register the ?win? register is used to access to the ddram for the window display area, where the start point is determined by the ?column address? and ?row address? instructions, and the end point by the ?window end column address ?and ?window end row address? instructions. the setting sequence for the window display area is listed as follows. for more detail, see (7) ?window addressing mode?. win=0 :window addressing mode off win=1 :window addressing mode on 1. set win=1, axi=1, and ayi=1 by ?increment control? instruction. 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode start address column address row address end address start address end address
NJU6820 - 61 - (31-10) power control csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 1 ampon halt dcon acl acl register the ?acl? register is used to initialize the internal power supply circuits. acl=0 : initialization off (normal) acl=1 : initialization on when the data of the ?acl register? is read out by the ?instruction register read? instruction, the read-out data is ?1? during the initialization and ?0? after the initialization. this initialization is performed by using the signal produced by 2 clocks on the osc 1 . for this reason, the wait time for 2 clocks of the osc 1 necessary until next instruction. dcon register the ?dcon? register is used to enable or disable the voltage booster. dcon=0 : voltage booster off dcon=1 : voltage booster on halt register the ?halt? register is used to enable or disable the power save mode. it is possible reduce operating current down to stand-by level. the internal status in the power save mode is listed below. halt=0 : power save off (normal) halt=1 : power save on internal status in the power save mode ? the oscillation circuits and internal power supply circuits are halted. ? all segment and common drivers output v ss level. ? the clock input into the osc 1 is inhibited. ? the display data in the ddram is maintained. ? the operational modes before the power save mode are maintained. ? the v 1 to v 4 and v lcd are in the high impedance. as a power save on sequence, the ?display off? must be executed first, next the ?power save on? instruction, and then all common and segment drivers output the v ss level. and as power save off sequence, the ?power save off? instruction is executed first, next the ?display on? instruction. if the ?power save off? instruction is executed in the display on status, unexpected pixels may instantly turn on. ampon register the ?ampon? register is used to enable or disable the voltage followers, voltage regulator and evr. ampon=0 : the voltage followers, voltage regulator the evr off ampon=1 : the voltage followers, voltage regulator the evr on
NJU6820 - 62 - (31-11) duty cycle ratio the ?duty cycle ratio? instruction is used to select lcd duty cycle ratio for the partial display function. the partial display function specifies some parts of display area on a lcd panel in the condition of lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. therefore, it is possible to optimize the lsi?s conditions with extremely low power consumption. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 0 ds 3 ds 2 ds 1 ds 0 duty cycle ratio ds 3 ds 2 ds 1 ds 0 dse=0 dse=1 row way displays 0 0 0 0 1/41 1/40 40 commons 0 0 0 1 1/37 1/36 37 commons 0 0 1 0 1/33 1/32 33 commons 0 0 1 1 1/29 1/28 29 commons 0 1 0 0 1/25 1/24 25 commons 0 1 0 1 1/21 1/20 21 commons 0 1 1 0 1/17 1/16 17 commons 0 1 1 1 1/13 1/12 13 commons 1 0 0 0 1/9 1/8 9 commons 1 0 0 1 1/5 1/4 5 commons 1 0 1 0 inhibited 1 0 1 1 inhibited 1 1 0 0 inhibited 1 1 0 1 inhibited 1 1 1 0 inhibited 1 1 1 1 inhibited the duty cycle ratio is controlled by the ?ds 3 to ds 0 ? registers of the ?duty cycle ratio? instruction and the ?dse? register of the ?display clock / duty-1? instruction. dse=?0? : the number of commons + 1 (duty cycle ratio in the default setting) dse=?1? : the number of commons (duty-1) when the ?dse? is ?0?, all common drivers output non-selective levels in period of last common. and the segment drivers output the same data for the last line as the data for previous line: for instance they output the same data for the 40 th and 41 th lines when the duty cycle ratio is set to 1/41. for the setting of the ?dse? register, see (31-17) ?display clock / duty-1?. (31-12) boost level the ?boost level? is used to select the multiple of the voltage booster for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 1 * vu 2 vu 1 vu 0 vu 2 vu 1 vu 0 boost level 0 0 0 1-time (no boost) 0 0 1 2-time 0 1 0 3-time 0 1 1 4-time 1 0 0 5-time 1 0 1 inhibited 1 1 0 inhibited 1 1 1 inhibited
NJU6820 - 63 - (31-13) lcd bias ratio the ?lcd bias ratio? is used to select the lcd bias ratio for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 1 0 * b 2 b 1 b 0 b 2 b 1 b 0 lcd bias ratio 0 0 0 1/8 0 0 1 1/7 0 1 0 1/6 0 1 1 1/5 1 0 0 1/4 1 0 1 inhibited 1 1 0 inhibited 1 1 1 inhibited (31-14) re flag the ?re flag? registers are used to determine the contents for the re registers (re 2 , re 1 and re 0 ) and it is possible to access to the instruction registers. the data in the ?tst 0 ? register must be ?0?, and it is used maker tests only. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst 0 re 2 re 1 re 0
NJU6820 - 64 - (31-15) gradation palette a, b and c csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 0 pa 03 / pa 83 pa 02 / pa 82 pa 01 / pa 81 pa 00 / pa 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 1 * * * pa 04 / pa 84 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 0 pa 13 / pa 93 pa 12 / pa 92 pa 11 / pa 91 pa 10 / pa 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 1 * * * pa 14 / pa 94 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 0 pa 23 / pa 103 pa 22 / pa 102 pa 21 / pa 101 pa 20 / pa 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 1 * * * pa 24 / pa 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 0 pa 33 / pa 113 pa 32 / pa 112 pa 31 / pa 111 pa 30 / pa 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 1 * * * pa 34 / pa 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 0 pa 43 / pa 123 pa 42 / pa 122 pa 41 / pa 121 pa 40 / pa 120
NJU6820 - 65 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 1 * * * pa 44 / pa 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 0 pa 53 / pa 133 pa 52 / pa 132 pa 51 / pa 131 pa 50 / pa 130 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 1 * * * pa 54 / pa 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 0 pa 63 / pa 143 pa 62 / pa 142 pa 61 / pa 141 pa 60 / pa 140 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 1 * * * pa 64 / pa 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 0 pa 73 / pa 153 pa 72 / pa 152 pa 71 / pa 151 pa 70 / pa 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 1 * * * pa 74 / pa 154 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 0 pb 03 / pb 83 pb 02 / pb 82 pb 01 / pb 81 pb 00 / pb 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 1 * * * pb 04 / pb 84
NJU6820 - 66 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 0 pb 13 / pb 93 pb 12 / pb 92 pb 11 / pb 91 pb 10 / pb 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 1 * * * pb 14 / pb 94 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 0 pb 23 / pb 103 pb 22 / pb 102 pb 21 / pb 101 pb 20 / pb 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 1 * * * pb 24 / pb 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 0 pb 33 / pb 113 pb 32 / pb 112 pb 31 / pb 111 pb 30 / pb 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 1 * * * pb 34 / pb 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 0 pb 43 / pb 123 pb 42 / pb 122 pb 41 / pb 121 pb 40 / pb 120 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 1 * * * pb 44 / pb 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 0 pb 53 / pb 133 pb 52 / pb 132 pb 51 / pb 131 pb 50 / pb 130
NJU6820 - 67 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 1 * * * pb 54 / pb 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 0 pb 63 / pb 143 pb 62 / pb 142 pb 61 / pb 141 pb 60 / pb 140 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 1 * * * pb 64 / pb 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 0 pb 73 / pb 153 pb 72 / pb 152 pb 71 / pb 151 pb 70 / pb 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 1 * * * pb 74 / pb 154 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 0 pc 03 / pc 83 pc 02 / pc 82 pc 01 / pc 81 pc 00 / pc 80 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 1 * * * pc 04 / pc 84 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 0 pc 13 / pc 93 pc 12 / pc 92 pc 11 / pc 91 pc 10 / pc 90 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 1 * * * pc 14 / pc 94
NJU6820 - 68 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 0 pc 23 / pc 103 pc 22 / pc 102 pc 21 / pc 101 pc 20 / pc 100 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 1 * * * pc 24 / pc 104 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 0 pc 33 / pc 113 pc 32 / pc 112 pc 31 / pc 111 pc 30 / pc 110 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 1 * * * pc 34 / pc 114 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 0 pc 43 / pc 123 pc 42 / pc 122 pc 41 / pc 121 pc 40 / pc 120 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 1 * * * pc 44 / pc 124 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 0 pc 53 / pc 133 pc 52 / pc 132 pc 51 / pc 131 pc 50 / pc 130 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 1 * * * pc 54 / pc 134 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 0 pc 63 / pc 143 pc 62 / pc 142 pc 61 / pc 141 pc 60 / pc 140
NJU6820 - 69 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 1 * * * pc 64 / pc 144 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 0 pc 73 / pc 153 pc 72 / pc 152 pc 71 / pc 151 pc 70 / pc 150 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 1 * * * pc 74 / pc 154 gradation palette table (variable gradation mode, pwm=?0? and mon=?0?) (palette aj, palette bj, palette cj, (j=0 to 15)) palette value gradation level note palette value gradation level note 0 0 0 0 0 0/31 gradation palette 0 initial value 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 gradation palette 8 initial value 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 gradation palette 1 initial value 1 0 0 1 1 19/31 gradation palette 9 initial value 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 gradation palette2 initial value 1 0 1 0 1 21/31 gradation palette 10 initial value 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 gradation palette 3 initial value 1 0 1 1 1 23/31 gradation palette 11 initial value 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 gradation palette 4 initial value 1 1 0 0 1 25/31 gradation palette 12 initial value 0 1 0 1 0 10/31 1 1 0 1 0 26/31 0 1 0 1 1 11/31 gradation palette 5 initial value 1 1 0 1 1 27/31 gradation palette 13 initial value 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 gradation palette 6 initial value 1 1 1 0 1 29/31 gradation palette 14 initial value 0 1 1 1 0 14/31 1 1 1 1 0 30/31 0 1 1 1 1 15/31 gradation palette 7 initial value 1 1 1 1 1 31/31 gradation palette 15 initial value
NJU6820 - 70 - (31-16) initial com line the ?initial com line? instruction is used to specify the common driver that starts scanning the display data. the line address, corresponding to the initial com line, is specified by the ?initial display line? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 0 sc 3 sc 2 sc 1 sc 0 sc3 sc2 sc1 sc0 initial com line (shift=0) initial com line (shift=1) 0 0 0 0 com 0 com 39 0 0 0 1 com 4 com 31 0 0 1 0 com 8 com 27 0 0 1 1 com 16 com 23 0 1 0 0 com 20 com 19 0 1 0 1 com 24 com 15 0 1 1 0 com 28 com 11 0 1 1 1 com 32 com 7 1 0 0 0 com 36 com 3 1 0 0 1 inhibited inhibited 1 0 1 0 inhibited inhibited 1 0 1 1 inhibited inhibited 1 1 0 0 inhibited inhibited 1 1 0 1 inhibited inhibited 1 1 1 0 inhibited inhibited 1 1 1 1 inhibited inhibited shift=0: positive scan direction (for instance, com 0 com 39 ) shift=1: negative scan direction (for instance, com 39 com 0 ) (31-17) display clock / duty-1 the ?display clock / duty-1? instruction is used to enable or disable the display clocks (cl, flm, fr, and clk), and to control on/off of the ?duty-1?. for more detail about the ?duty-1?, see (31-11) ?duty cycle ratio?. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 1 * * dse son son=0: cl, flm, fr, and clk outputs level ?0?. son=1: cl, flm, fr, and clk outputs are active. dse=0: duty -1 off dse=1: duty -1 on
NJU6820 - 71 - (31-18) gradation mode control the ?gradation mode control? is used select display mode as follows. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 0 pwm c256 * * pwm register pwm=0: variable gradation mode (variable 16-gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) c256 register c256=0 256-color mode off (4,096-color in the default setting) c256=1 256-color mode on (31-19) data bus length the ?data bus length? instruction is used to select the 8- or 16- bit data bus length and determine the internal or external oscillation. in the 16-bit data bus mode, instruction data must be 16-bit (d 15 to d 0 ) as well as display data. however, for the access to the instruction registers, the lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 1 hsw abs cks wls hsw register hsw =0: high speed access mode off hsw=1: high speed access mode on (only in the 8-bit data bus length) abs register abs=0: abs mode off (normal) abs=1: abs mode on wls register wls=0: 8-bit data bus length wls =1: 16-bit data bus length cks register cks =0: internal oscillation (the osc 1 terminal must be fixd ?1? or ?0?.) cks =1: external oscillation (by the external clock into the osc 1 or external resister between the osc 1 and osc 2 . osc 2 should be open when clock is inputted from osc 1 .)
NJU6820 - 72 - (31-20) evr control the ?evr control? instruction is used to fine-tune the lcd driving voltage (v lcd ) so that it is possible to optimize the contrast level for a lcd panel. this instruction must be programmed by upper 3-bit data first, next lower 4-bit data. and it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the vlcd from being generated. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 0 dv 3 dv 2 dv 1 dv 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 1 * dv 6 dv 5 dv 4 dv 6 dv 5 dv 4 dv 3 dv 2 dv 1 dv 0 v lcd 0 0 0 0 0 0 0 low 0 0 0 0 0 0 1 : : : : : 1 1 1 1 1 1 1 high the formula of the v lcd is shown below. v lcd [v] = 0.5 x v reg + m (v reg ? 0.5 x v reg ) / 127 v ba = v ee x 0.9 v ba : output voltage of the reference voltage generator v reg = v ref x n v ref : input voltage of the voltage regulator v reg : output voltage of the voltage regulator n : register value for the voltage booster m : register value for the evr
NJU6820 - 73 - (31-21) frequency control the ?frequency control? instruction is used to control the frame frequency for a lcd panel. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 1 * rf 2 rf 1 rf 0 rfx register (x=0, 1, 2) the ?rfx? register is used to determine the feed back resister value for the internal oscillator and it is possible to adjust the frame frequency for the lcd modules. rf 2 rf 1 rf 0 feedback resistor value 0 0 0 reference value 0 0 1 0.8 x reference value 0 1 0 0.9 x reference value 0 1 1 1.1 x reference value 1 0 0 1.2 x reference value 1 0 1 0.7 x reference value 1 1 0 1.3 x reference value 1 1 1 inhibited (31-22) discharge on/off discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and the v lcd terminals. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 1 0 * * dis2 dis dis=0: discharge off (capacitors on the v lcd , v 1 , v 2 , v 3 and v 4 ) dis=1: discharge on (capacitors on the v lcd , v 1 , v 2 , v 3 and v 4 ) dis2=0: discharge off (resistance between v out and v ee ) dis2=1: discharge on (resistance between v out and v ee ) note ) v out and v ee are internally connected with the resistor (100k ? typical) in the power-on .
NJU6820 - 74 - (31-23) instruction register address the ?instruction register address? is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the ?instruction register read? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 0 ra 3 ra 2 ra 1 ra 0 (31-24) instruction register read the ?instruction register read? instruction is used to read out the contents of the instruction register in combination with the ?instruction register address? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0/1 0/1 0/1 * * * * internal register data read (31-25) window end column address the ?window end column address? is used to specify the column address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 0 ex 3 ex 2 ex 1 ex 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 1 ex 7 ex 6 ex 5 ex 4 (31-26) window end row address set the ?window end row address? is used to specify the row address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 2-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 0 ey 3 ey 2 ey 1 ey 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 1 * * ey 5 ey 4
NJU6820 - 75 - (31-27) initial reverse line the ?initial reverse line? instruction is used to specify the initial reverse line address for the reverse line display. lower 4-bit data must be programmed first, next upper 2-bit data. it is programmed in between 00 h and 27 h and the line address beyond 27 h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 0 ls 3 ls 2 ls 1 ls 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 1 * * ls 5 ls 4 (31-28) last reverse line the ?last reverse line? instruction is used to specify the last reverse line address for the reverse line display. lower 4-bit must be programmed first, next upper 2-bit data. it is programmed in between 00 h and 27 h and the line address beyond 27 h is inhibited. the address relation: lsi < lei (i=7 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 0 le 3 le 2 le 1 le 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 1 * * le 5 le 4 (31-29) reverse line display on/off the ?reverse line display on/off? is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev lrev register the ?lrev? register is used to enable or disable the reverse line display. lrev =0: reverse line display off (normal) lrev =1: reverse line display on
NJU6820 - 76 - bt register the ?bt? register is used to determine the reverse line display mode in the reverse line display on (lrev=1) status. bt =0: normal reverse line display bt =1: blink once every 32 frames display examples in the lrev=?1? and bt=?1? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? njrc lcd driver low power and low voltage njrc lcd driver low power and low voltage (31-30) gradation palette setting control csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 1 * * * ps ps register ps=0: lower 8 gradation setting ps=1: upper 8 gradation setting blink once every 32 frames initial reverse line address last reverse line address blink once every 32 frames
NJU6820 - 77 - (31-31) pwm control the ?pwm control? is used to determine the pwm type for the segment waveforms, where the type can be specified for each of the segai, segbi and segci (i=0-127) drivers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 1 0 pwms pwma pwmb pwmc pwms register pwms=0: type 1 pwms=1: type 2 pwma, b and c registers the ?pwma, pwmb and pwmc? registers are used to select the type 1-o or type 1-e. pwmz=0 (z=a, b and c): type 1-o pwmz=1 (z=a, b and c): type 1-e pwm type1 (pwms=?0?) pwm type2 (pwms=?1?) odd line even line ?h? ?l? v lcd v 2 v 2 type-o type-e cl seg v lcd ?h? ?l? cl seg v 2 v lcd
NJU6820 - 78 - (32) the relationship between common drivers and row addresses row address assignment of common drivers is programmed by the ? shift ? register of the ? display control (1) ? , ? duty cycle ratio ?, ? internal display line ? and ? initial com line ? instructions. when initial display line is ?0? if the ? shift ? is ? 0 ?, the scan direction is normal. when the ? la 0 to la 6 ? registers of the ? initial display line ?instruction is ? 0 ?, the ? my ? corresponding to the initial com line is ? 0 ? and is increasing during display. when initial display line is not ?0? if the ? shift ? is ? 1 ?, the scan direction is inversed. when the ? la 0 to la 6 ? registers of the ? initial display line ?instruction is not ? 0 ?, the ? my ? corresponding to the initial com line is this setting value and is increasing during display. the following are examples of setting the start-line 0 or 5 at 1/41, 1/17, or 1/17 duty.
NJU6820 - 79 - (32-1) initial display line ?0?, 1/41 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 0 36 32 28 24 20 16 12 8 4 com 1 com 2 com 3 39 com 4 0 com 5 com 6 com 7 39 com 8 0 com 9 com 10 com 11 39 com 12 0 com 13 com 14 com 15 39 com 16 0 com 17 com 18 com 19 39 com 20 0 com 21 com 22 com 23 39 com 24 0 com 25 com 26 com 27 39 com 28 0 com 29 com 30 com 31 39 com 32 0 com 33 com 34 com 35 39 com 36 0 com 37 com 38 com 39 39 35 31 27 23 19 15 11 7 3 (40 rd com period) *1 39 39 39 39 39 39 39 39 39 39 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 40 th com period is not selected. (32-2) initial display line ?0?, 1/41 duty cycle (common backward scan) shift=?1?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 39 3 7 11 15 19 23 27 31 35 com 1 com 2 com 3 0 com 4 39 com 5 com 6 com 7 0 com 8 39 com 9 com 10 com 11 0 com 12 39 com 13 com 14 com 15 0 com 16 39 com 17 com 18 com 19 0 com 20 39 com 21 com 22 com 23 0 com 24 39 com 25 com 26 com 27 39 com 28 0 com 29 com 30 com 31 39 com 32 0 com 33 com 34 com 35 39 com 36 0 com 37 com 38 com 39 0 4 8 12 16 20 24 28 32 36 (40 rd com period) *1 39 39 39 39 39 39 39 39 39 39 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 40 th com period is not selected.
NJU6820 - 80 - (32-3) initial display line ?0?, 1/17 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0110?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 0 12 8 4 com 1 com 2 com 3 15 com 4 0 com 5 com 6 com 7 15 com 8 0 com 9 com 10 com 11 15 com 12 0 com 13 com 14 com 15 15 com 16 0 com 17 com 18 com 19 15 com 20 0 com 21 com 22 com 23 15 com 24 0 com 25 com 26 com 27 15 com 28 0 com 29 com 30 com 31 15 com 32 0 com 33 com 34 com 35 15 com 36 0 com 37 com 38 com 39 15 11 7 3 (17 rd com period) *1 16 16 16 16 16 16 16 16 16 16 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 17 th com period is not selected. (32-4) initial display line ?0?, 1/17 duty cycle (common backward scan) shift=?1?(common forward scan), ds 3 , 2 , 1 , 0 =?0110?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 15 11 7 3 com 1 com 2 com 3 0 com 4 15 com 5 com 6 com 7 0 com 8 15 com 9 com 10 com 11 0 com 12 15 com 13 com 14 com 15 0 com 16 15 com 17 com 18 com 19 0 com 20 15 com 21 com 22 com 23 0 com 24 15 com 25 com 26 com 27 0 com 28 0 com 29 com 30 com 31 0 com 32 0 com 33 com 34 com 35 0 com 36 0 com 37 com 38 com 39 0 12 8 4 (17 rd com period) *1 16 16 16 16 16 16 16 16 16 16 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 17 th com period is not selected.
NJU6820 - 81 - (32-5) initial display line ?0?, 1/5 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?1001?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 0 com 1 com 2 com 3 3 com 4 0 com 5 com 6 com 7 3 com 8 0 com 9 com 10 com 11 3 com 12 0 com 13 com 14 com 15 3 com 16 0 com 17 com 18 com 19 3 com 20 0 com 21 com 22 com 23 3 com 24 0 com 25 com 26 com 27 3 com 28 0 com 29 com 30 com 31 3 com 32 0 com 33 com 34 com 35 3 com 36 0 com 37 com 38 com 39 3 (5 rd com period) *1 4 4 4 4 4 4 4 4 4 4 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 5 th com period is not selected. (32-6) initial display line ?0?, 1/5 duty cycle (common forward scan) shift=?1?(common forward scan), ds 3 , 2 , 1 , 0 =?1001?, la 7 ?.la 0 =?00000000?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 3 com 1 com 2 com 3 0 com 4 3 com 5 com 6 com 7 0 com 8 3 com 9 com 10 com 11 0 com 12 3 com 13 com 14 com 15 0 com 16 3 com 17 com 18 com 19 0 com 20 3 com 21 com 22 com 23 0 com 24 3 com 25 com 26 com 27 0 com 28 3 com 29 com 30 com 31 0 com 32 3 com 33 com 34 com 35 0 com 36 3 com 37 com 38 com 39 0 (5 rd com period) *1 4 4 4 4 4 4 4 4 4 4 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 5 rd com period is not selected.
NJU6820 - 82 - (33) initial display line ?5?, 1/41 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000101?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 5 1 37 33 29 25 21 17 13 9 com 1 com 2 39 com 3 0 com 4 5 com 5 com 6 39 com 7 0 com 8 5 com 9 com 10 39 com 11 0 com 12 5 com 13 com 14 39 com 15 0 com 16 5 com 17 com 18 39 com 19 0 com 20 5 com 21 com 22 39 com 23 0 com 24 5 com 25 com 26 39 com 27 0 com 28 5 com 29 com 30 39 com 31 0 com 32 5 com 33 com 34 39 com 35 0 com 36 5 com 37 com 38 39 com 39 4 0 36 32 28 24 20 16 12 8 (40 rd com period) *1 39 39 39 39 39 39 39 39 39 39 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 40 th com period is not selected. (33-1) initial display line ?5?, 1/41 duty cycle (common backward scan) shift=?1?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000101?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 4 0 36 32 28 24 20 16 12 8 com 1 39 com 2 com 3 com 4 0 com 5 39 com 6 com 7 com 8 0 com 9 39 com 10 com 11 com 12 0 com 13 39 com 14 com 15 com 16 0 com 17 39 com 18 com 19 com 20 0 com 21 39 com 22 com 23 com 24 0 com 25 39 com 26 com 27 com 28 0 com 29 39 com 30 com 31 com 32 0 com 33 39 com 34 com 35 com 36 0 com 37 39 com 38 com 39 5 1 37 33 29 25 21 17 13 9 (40 rd com period) *1 39 39 39 39 39 39 39 39 39 39 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 40 th com period is not selected.
NJU6820 - 83 - (33-2) initial display line ?5?, 1/17 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0110?, la 7 ?.la 0 =?00000101?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 5 17 13 9 com 1 com 2 com 3 20 com 4 5 com 5 com 6 com 7 20 com 8 5 com 9 com 10 com 11 20 com 12 5 com 13 com 14 com 15 20 com 16 5 com 17 com 18 com 19 20 com 20 5 com 21 com 22 com 23 20 com 24 5 com 25 com 26 com 27 20 com 28 5 com 29 com 30 com 31 20 com 32 5 com 33 com 34 com 35 20 com 36 5 com 37 com 38 com 39 20 16 12 8 (17 rd com period) *1 16 16 16 16 16 16 16 16 16 16 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 17 th com period is not selected. (33-3) initial display line ?5?, 1/17 duty cycle (common backward scan) shift=?1?(common forward scan), ds 3 , 2 , 1 , 0 =?0110?, la 7 ?.la 0 =?00000101?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 20 16 12 8 com 1 com 2 com 3 5 com 4 20 com 5 com 6 com 7 5 com 8 20 com 9 com 10 com 11 5 com 12 20 com 13 com 14 com 15 5 com 16 20 com 17 com 18 com 19 5 com 20 20 com 21 com 22 com 23 5 com 24 20 com 25 com 26 com 27 5 com 28 20 com 29 com 30 com 31 5 com 32 20 com 33 com 34 com 35 5 com 36 20 com 37 com 38 com 39 5 17 13 9 (17 rd com period) *1 16 16 16 16 16 16 16 16 16 16 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 17 th com period is not selected.
NJU6820 - 84 - (33-4) initial display line ?5?, 1/5 duty cycle (common forward scan) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?1001?, la 7 ?.la 0 =?00000101?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 5 com 1 com 2 com 3 8 com 4 5 com 5 com 6 com 7 8 com 8 5 com 9 com 10 com 11 8 com 12 5 com 13 com 14 com 15 8 com 16 5 com 17 com 18 com 19 8 com 20 5 com 21 com 22 com 23 8 com 24 5 com 25 com 26 com 27 8 com 28 5 com 29 com 30 com 31 8 com 32 5 com 33 com 34 com 35 8 com 36 5 com 37 com 38 com 39 8 (5 rd com period) *1 4 4 4 4 4 4 4 4 4 4 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 5 th com period is not selected. (33-5) initial display line ?5?, 1/5 duty cycle (common forward scan) shift=?1?(common forward scan), ds 3 , 2 , 1 , 0 =?1001?, la 7 ?.la 0 =?00000101?(initial display line 0) sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 8 com 1 com 2 com 3 5 com 4 8 com 5 com 6 com 7 5 com 8 8 com 9 com 10 com 11 5 com 12 8 com 13 com 14 com 15 5 com 16 8 com 17 com 18 com 19 5 com 20 8 com 21 com 22 com 23 5 com 24 8 com 25 com 26 com 27 5 com 28 8 com 29 com 30 com 31 5 com 32 8 com 33 com 34 com 35 5 3 com 36 8 com 37 com 38 com 39 5 (5 rd com period) *1 4 4 4 4 4 4 4 4 4 4 ds: duty cycle ratio, sc: initial com line, la: initial display line *1 : 5 th com period is not selected.
NJU6820 - 85 - (33-6) initial display line ?0?, 1/40 duty cycle (common forward scan, dse=?1?) shift=?0?(common forward scan), ds 3 , 2 , 1 , 0 =?0000?, la 7 ?.la 0 =?00000000?(initial display line 0) dse=?1? sc 3 sc 2 sc 1 sc 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 inhibited inhibited inhibited inhibited inhibited inhibited com 0 0 36 32 28 24 20 16 12 8 4 com 1 com 2 com 3 39 com 4 0 com 5 com 6 com 7 39 com 8 0 com 9 com 10 com 11 39 com 12 0 com 13 com 14 com 15 39 com 16 0 com 17 com 18 com 19 39 com 20 0 com 21 com 22 com 23 39 com 24 0 com 25 com 26 com 27 39 com 28 0 com 29 com 30 com 31 39 com 32 0 com 33 com 34 com 35 39 com 36 0 com 37 com 38 com 39 39 35 31 27 23 19 15 11 7 3 ds: duty cycle ratio, sc: initial com line, la: initial display line
NJU6820 - 86 - absolute maximum ratings parameter symbol condition terminal rating unit supply voltage (1) v dd v dd -0.3 to +4.0 v supply voltage (2) v ee v ee -0.3 to +4.0 v supply voltage (3) v out v out -0.3 to +19.0 v supply voltage (4) v reg v reg -0.3 to +19.0 v supply voltage (5) v lcd v lcd -0.3 to +19.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 -0.3 to v lcd + 0.3 v input voltage v i v ss =0v ta = +25 c *1 -0.3 to v dd + 0.3 v storage temperature t stg -45 to +125 c note 1) d 0 to d 15 , csb, rs, rdb, wrb, osc 1 , resb, test 1, test 2 , terminals. recommended operating conditions parameter symbol terminal min typ max unit note v dd1 1.7 3.3 v *1 v dd2 v dd 2.4 3.3 v *2 supply voltage v ee v ee 2.4 3.3 v *3 v lcd v lcd 5 18.0 v *4 v out v out 18.0 v v reg v reg v out 0.9 v operating voltage v ref v ref 2.1 3.3 v *5 operating temperature t opr -30 85 c note1) applies to the condition when the reference voltage generator is not used. note2) applies to the condition when the reference voltage generator is used. note3) applies to the condition when the voltage booster is used. note4) the following relationship among the supply voltages must be maintained. v ss NJU6820 - 87 - dc characteristics 1 v ss = 0v, v dd = +1.7 to +3.3v, ta = -30 to +85 c parameter sym bol condition min typ max unit note high level input voltage v ih 0.8 v dd v dd v *1 low level input voltage v il 0 0.2v dd v *1 high level output voltage v oh1 i oh = -0.4ma v dd - 0.4 v *2 low level output voltage v ol1 i ol = 0.4ma 0.4 v *2 high level output voltage v oh2 i oh = -0.1ma v dd - 0.4 v *3 low level output voltage v ol2 i ol = 0.1ma 0.4 v *3 input leakage current i li v i = v ss or v dd -10 10 a *4 output leakage current i lo v i = v ss or v dd -10 10 a *5 v lcd = 10v 1 2 driver on-resistance r on1 | ? v on | = 0.5v v lcd = 6v 2 4 k ? *6 stand-by current i stb csb=h, ta=25 c v dd = 3v 15 a *7 f osc1 152 186 220 *8 f osc2 34 42 50 *9 internal oscillation frequency f osc3 v dd = 3v ta = 2 5 c 4.9 6.0 7.1 khz *10 f r1 rf=51k ? 172 f r2 rf=240k ? 40 external oscillation frequency f r3 rf=1800k ? 5.5 khz *11 voltage converter output voltage v out n-time booster (n=2 to 5) rl = 500k ? (v out - v ss ) (n x v ee ) x 0.95 v *12 supply current (1) i dd1 v dd = 3v, 5-time booster whole on pattern 520 780 supply current (2) i dd2 v dd = 3v, 5-time booster checker pattern 650 980 supply current (3) i dd3 v dd = 3v,4-time booster whole on pattern 360 540 supply current (4) i dd4 v dd = 3v, 4-time booster checker pattern 450 680 a *13 v ba operating voltage v ba v ee = 2.4 to 3.3v (0.9 v ee ) x 0.98 0.9 v ee (0.9 v ee ) x 1.02 v *14 v reg operating voltage v reg v ee = 2.4 to 3.3v v ref = 0.9 x v ee n-time booster (n=2 to 5) (v ref x n) x 0.97 (v ref x n) (v ref x n) x 1.03 v *15 v 2 -100 0 +100 v 3 -100 0 +100 v d12 -30 0 +30 v d34 -30 0 +30 output voltage v d24 -30 0 +30 mv *16
NJU6820 - 88 - clock and frame frequency display duty cycle ratio (1/d) parameter symbol display mode 1/41 to 1/25 1/21 to 1/13 1/9 1/5 note 16 gradation mode f osc / (62xd) f osc / (62xdx2) f osc / (62xdx4) f osc / (62xdx8) simplified 8 gradation mode f osc / (14xd) f osc / (14xdx2) f osc / (14xdx4) f osc / (14xdx8) internal clock f osc b&w mode f osc / (2xd) f osc / (2xdx2) f osc / (2xdx4) f osc / (2xdx8) 16 gradation mode f ck / (62xd) f ck / (62xdx2) f ck / (62xdx4) f ck / (62xdx8) simplified 8 gradation mode f ck / (14xd) f ck / (14xdx2) f ck / (14xdx4) f ck / (14xdx8) external clock f ck b&w mode f ck / (2xd) f ck / (2xdx2) f ck / (2xdx4) f ck / (2xdx8) flm
NJU6820 - 89 - applied terminals and conditions note 1) d 0 -d 15 , csb, rs, rdb, wrb, p/s, sel68, resb note 2) d 0 -d 15 note 3) cl, flm, fr, clk note 4) csb, rs, sel68, rdb, wrb, p/s, resb, osc 1 note 5) d 0 -d 15 in the high impedance note 6) sega 0 -sega 127 , segb 0 -segb 127 , segc 0 -segc 127 , com 0 -com 39 - defines the resistance between the com/seg terminals and each of the power supply terminals (v lcd , v 1 , v 2 , v 3 and v 4 ) at the condition of 0.5v deference and 1/8 lcd bias ratio. note 7) v dd - the oscillator is halted, csb=?1? (disabled), no-load on the com/seg drivers note 8) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the variable gradation mode. note 9) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the fixed gradation mode. note 10) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the black & white mode. note 11) v dd =3v, ta=25 c note 12) v out - applies to the condition when the internal voltage booster, the internal oscillator and internal power circuits are used. - v ee =2.4v to 3.3v, evr= (1,1,1,1,1,1,1), 1/4 to 1/8 lcd bias, 1/41 duty cycle, no-load on com/seg drivers - rl=500k ? between the v out and the v ss , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1? note 13) v dd - applies to the condition using the internal oscillator and internal power circuits, no access between the lsi and mpu. - evr= (1,1,1,1,1,1,1), all pixels turned-on or checkerboard display in gradation mode. no-load on the com/seg drivers. - v dd =v ee , v ref =0.9v ee , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1?, nlin=?0? 1/41 duty cycle, ta=25 c note 14) v ba - applies to the condition that v ba =v ref and voltage booster n= 1. dcon=?0?, v out =13.5v input. note 15) v reg - v ee =2.4v to 3.3v, v ref =0.9v ee , v out =18v, 1/4 to 1/8 lcd bias ratio, 1/41 duty cycle, evr=(1,1,1,1,1,1,1) - checkerboard display, no-load on the com/seg drivers, the voltage booster n=2 to 5 ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1?, nlin=?0? note 16) v lcd , v 1 , v 2 , v 3 , v 4 - v ee =3.0v, v ref =0.9v ee , v out =15v, 1/4 to 1/8 lcd bias, evr= (1,1,1,1,1,1,1), display off, no- load on the com/seg drivers, voltage booster n=5, ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1? v d12 : (1)-(2) v d34 : (3)-(4) v d24 : (2)-(4) (1) (2) (3) (4) v lcd v 1 v 2 v 3 v 4 v ss
NJU6820 - 90 - ac characteristics write operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 90 35 35 ns ns ns wrb data setup time data hold time t ds8 t dh8 30 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 160 70 70 ns ns ns wrb data setup time data hold time t ds8 t dh8 40 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 180 80 80 ns ns ns wrb data setup time data hold time t ds8 t dh8 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb wrb rs d 0 to d 15 t ah8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8
NJU6820 - 91 - read operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 250 120 120 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 110 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb rs d 0 to d 15 t rdd8 t rdh8 t cyc8 rdb t wrlr8 t wrhr8 t ah8
NJU6820 - 92 - write operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 90 35 35 ns ns ns e data setup time data hold time t ds6 t dh6 40 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 160 70 70 ns ns ns e data setup time data hold time t ds6 t dh6 50 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 180 80 80 ns ns ns e data setup time data hold time t ds6 t dh6 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w (wrb) d 0 to d 15 t ehw6 t elw6 t ds6 t dh6 t cyc6 e (rdb)
NJU6820 - 93 - read operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 250 120 120 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 110 ns ns d0 to d15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w (wrb) d 0 to d 15 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 e (rdb)
NJU6820 - 94 - serial interface (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 50 20 20 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 50 20 20 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 80 35 35 ns ns ns scl address setup time address hold time t ass t ahs 35 35 ns ns rs data setup time data hold time t dss t dhs 35 35 ns ns sda csb ? scl time csb hold time t css t csh 35 35 ns ns csb note) each timing is specified based on 20% and 80% of v dd . t css csb rs t csh sda t slw t shw t dss t dhs t cycs scl t a hs t ass
NJU6820 - 95 - display control timing output timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 500 ns flm fr delay time t fr 0 500 ns fr cl delay time t dcl 0 200 ns cl output timing (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm cl=15pf 0 1000 ns flm fr delay time t fr 0 1000 ns fr cl delay time t dcl 0 200 ns cl note) each timing is specified based on 20% and 80% of v dd . cl t dflm t fr flm t dflm fr clk t dcl
NJU6820 - 96 - input clock timing (v dd =1.7 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal osc 1 ?h? level pulse width (1) t ckhw1 2.27 3.29 s osc 1 ?l? level pulse width (1) t cklw1 2.27 3.29 s osc 1 ? 1 osc 1 ?h? level pulse width (2) t ckhw2 10 14.7 s osc 1 ?l? level pulse width (2) t cklw2 10 14.7 s osc 1 ? 2 osc 1 ?h? level pulse width (3) t ckhw3 70 103 s osc 1 ?l? level pulse width (3) t cklw3 70 103 s osc 1 ? 3 note) each timing is specified based on 20% and 80% of v dd . note 1) applied to the variable gradation / mode mon=?0?,pwm=?0? note 2) applied to the fixed gradation / mode mon=?0?,pwm=?1? note 3) applied to the b&w mode / mon=?1? osc 1 t cklw t ckhw
NJU6820 - 97 - reset input timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.0 s resb ?l? level pulse width t rw 10.0 s resb (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.5 s resb ?l? level pulse width t rw 10.0 s resb note) each timing is specified based on 20% and 80% of v dd . t rw res b internal circuit status end of reset during reset t r
NJU6820 - 98 - typical characteristic parameter symbol min typ max unit basic delay time of gate ta=+25 c, v ss =0v, v dd =3.0v 10 ns input output terminal type (a) input circuit terminals: csb, rs, rdb, wrb, sel68, p/s, resb (b) output circuit terminals: flm, cl, fr, clk (c) input/output circuit terminals: d 0 to d 15 v dd i v ss (0v) input signal o v dd v ss (0v) output control signal output signal i/o v dd v ss (0v) input signal v dd v ss (0v) output control signal output signal v ss (0v) input control signal
NJU6820 - 99 - (d) display output circuit terminals: sega 0 to sega 127 segb 0 to segb 127 segc 0 to segc 127 com 0 to com 39 o v lcd v ss (0v) output control signal 1 v 1 /v 2 v ss (0v) output control signal 3 v lcd v ss (0v) v 3 /v 4 output control signal 2 output control signal 4 v lcd
NJU6820 - 100 - application circuit examples (1) mpu connections 80-type mpu interface 68-type mpu interface serial interface a 0 v cc a 1 to a 7 iorq d 0 to d 7 rd wr res gnd 7 decoder rs csb d 0 to d 7 rdb wr b res b v dd v ss 8 reset 1.7v to 3.3v (80-type mpu) NJU6820 a 0 v cc a 1 to a 15 vm a d 0 to d 7 e r/w res gnd 15 decoder rs csb d 0 to d 7 rdb ( e ) wrb ( r/w ) resb v dd v ss 8 reset 1.7v to 3.3v (68-type mpu) NJU6820 a 0 v cc a 1 to a 7 port 1 port 2 res gnd 7 decoder rs csb sd a scl resb v dd v ss reset 1.7v to 3.3v ( mpu ) NJU6820
NJU6820 - 101 [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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